cy62256vso.tan.qmsg

用VHDL编写的CY62256VSO芯片的驱动程序.

{ "Info" "ITDB_FULL_TPD_RESULT" "FPGACS CS 8.100 ns Longest " "Info: Longest tpd from source pin \"FPGACS\" to destination pin \"CS\" is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns FPGACS 1 PIN PIN_140 53 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_140; Fanout = 53; PIN Node = 'FPGACS'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FPGACS } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.800 ns) 7.100 ns FPGACS~16 2 COMB LC27 1 " "Info: 2: + IC(3.600 ns) + CELL(2.800 ns) = 7.100 ns; Loc. = LC27; Fanout = 1; COMB Node = 'FPGACS~16'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.400 ns" { FPGACS FPGACS~16 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 8.100 ns CS 3 PIN PIN_172 0 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 8.100 ns; Loc. = PIN_172; Fanout = 0; PIN Node = 'CS'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { FPGACS~16 CS } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 55.56 % ) " "Info: Total cell delay = 4.500 ns ( 55.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 44.44 % ) " "Info: Total interconnect delay = 3.600 ns ( 44.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.100 ns" { FPGACS FPGACS~16 CS } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.100 ns" { FPGACS {} FPGACS~out {} FPGACS~16 {} CS {} } { 0.000ns 0.000ns 3.600ns 0.000ns } { 0.000ns 0.700ns 2.800ns 1.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "FPGADT\[0\]~reg0 DATA\[0\] GLBCLK -2.900 ns register " "Info: th for register \"FPGADT\[0\]~reg0\" (data pin = \"DATA\[0\]\", clock pin = \"GLBCLK\") is -2.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GLBCLK destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"GLBCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns GLBCLK 1 CLK PIN_184 18 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { GLBCLK } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns FPGADT\[0\]~reg0 2 REG LC9 5 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC9; Fanout = 5; REG Node = 'FPGADT\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { GLBCLK FPGADT[0]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK FPGADT[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} FPGADT[0]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[0\] 1 PIN PIN_173 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_173; Fanout = 1; PIN Node = 'DATA\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[0] } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns DATA\[0\]~31 2 COMB IO1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = IO1; Fanout = 2; COMB Node = 'DATA\[0\]~31'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.700 ns" { DATA[0] DATA[0]~31 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 5.900 ns FPGADT\[0\]~reg0 3 REG LC9 5 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 5.900 ns; Loc. = LC9; Fanout = 5; REG Node = 'FPGADT\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { DATA[0]~31 FPGADT[0]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 49.15 % ) " "Info: Total cell delay = 2.900 ns ( 49.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 50.85 % ) " "Info: Total interconnect delay = 3.000 ns ( 50.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { DATA[0] DATA[0]~31 FPGADT[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { DATA[0] {} DATA[0]~31 {} FPGADT[0]~reg0 {} } { 0.000ns 0.000ns 3.000ns } { 0.000ns 0.700ns 2.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK FPGADT[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} FPGADT[0]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { DATA[0] DATA[0]~31 FPGADT[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { DATA[0] {} DATA[0]~31 {} FPGADT[0]~reg0 {} } { 0.000ns 0.000ns 3.000ns } { 0.000ns 0.700ns 2.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 18:06:39 2009 " "Info: Processing ended: Thu Jan 08 18:06:39 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}