cy62256vso.tan.qmsg

用VHDL编写的CY62256VSO芯片的驱动程序.

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "GLBCLK " "Info: Assuming node \"GLBCLK\" is an undefined clock" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 9 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "GLBCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "GLBCLK register DATA\[7\]~reg0 register DATA\[7\]~reg0 116.28 MHz 8.6 ns Internal " "Info: Clock \"GLBCLK\" has Internal fmax of 116.28 MHz between source register \"DATA\[7\]~reg0\" and destination register \"DATA\[7\]~reg0\" (period= 8.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest register register " "Info: + Longest register to register delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[7\]~reg0 1 REG LC101 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA\[7\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[7]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 5.200 ns DATA\[7\]~reg0 2 REG LC101 5 " "Info: 2: + IC(3.000 ns) + CELL(2.200 ns) = 5.200 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA\[7\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { DATA[7]~reg0 DATA[7]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 42.31 % ) " "Info: Total cell delay = 2.200 ns ( 42.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 57.69 % ) " "Info: Total interconnect delay = 3.000 ns ( 57.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { DATA[7]~reg0 DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.200 ns" { DATA[7]~reg0 {} DATA[7]~reg0 {} } { 0.000ns 3.000ns } { 0.000ns 2.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GLBCLK destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"GLBCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns GLBCLK 1 CLK PIN_184 18 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { GLBCLK } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns DATA\[7\]~reg0 2 REG LC101 5 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA\[7\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GLBCLK source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"GLBCLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns GLBCLK 1 CLK PIN_184 18 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { GLBCLK } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns DATA\[7\]~reg0 2 REG LC101 5 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA\[7\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { DATA[7]~reg0 DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.200 ns" { DATA[7]~reg0 {} DATA[7]~reg0 {} } { 0.000ns 3.000ns } { 0.000ns 2.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DATA\[7\]~reg0 FPGACS GLBCLK 6.200 ns register " "Info: tsu for register \"DATA\[7\]~reg0\" (data pin = \"FPGACS\", clock pin = \"GLBCLK\") is 6.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns FPGACS 1 PIN PIN_140 53 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_140; Fanout = 53; PIN Node = 'FPGACS'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FPGACS } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.200 ns) 6.500 ns DATA\[7\]~reg0 2 REG LC101 5 " "Info: 2: + IC(3.600 ns) + CELL(2.200 ns) = 6.500 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA\[7\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { FPGACS DATA[7]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 44.62 % ) " "Info: Total cell delay = 2.900 ns ( 44.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 55.38 % ) " "Info: Total interconnect delay = 3.600 ns ( 55.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { FPGACS DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { FPGACS {} FPGACS~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 0.700ns 2.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GLBCLK destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"GLBCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns GLBCLK 1 CLK PIN_184 18 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { GLBCLK } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns DATA\[7\]~reg0 2 REG LC101 5 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC101; Fanout = 5; REG Node = 'DATA\[7\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { FPGACS DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { FPGACS {} FPGACS~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 0.700ns 2.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[7]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "GLBCLK DATA\[0\] DATA\[0\]~en 10.700 ns register " "Info: tco from clock \"GLBCLK\" to destination pin \"DATA\[0\]\" through register \"DATA\[0\]~en\" is 10.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GLBCLK source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"GLBCLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns GLBCLK 1 CLK PIN_184 18 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 18; CLK Node = 'GLBCLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { GLBCLK } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns DATA\[0\]~en 2 REG LC6 11 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC6; Fanout = 11; REG Node = 'DATA\[0\]~en'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { GLBCLK DATA[0]~en } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[0]~en } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[0]~en {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest register pin " "Info: + Longest register to pin delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[0\]~en 1 REG LC6 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 11; REG Node = 'DATA\[0\]~en'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[0]~en } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(4.000 ns) 7.000 ns DATA\[0\] 2 PIN PIN_173 0 " "Info: 2: + IC(3.000 ns) + CELL(4.000 ns) = 7.000 ns; Loc. = PIN_173; Fanout = 0; PIN Node = 'DATA\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { DATA[0]~en DATA[0] } "NODE_NAME" } } { "CY62256VSO.vhd" "" { Text "E:/CY62256VSO/CY62256VSO.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 57.14 % ) " "Info: Total cell delay = 4.000 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 42.86 % ) " "Info: Total interconnect delay = 3.000 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { DATA[0]~en DATA[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { DATA[0]~en {} DATA[0] {} } { 0.000ns 3.000ns } { 0.000ns 4.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { GLBCLK DATA[0]~en } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { GLBCLK {} GLBCLK~out {} DATA[0]~en {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { DATA[0]~en DATA[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { DATA[0]~en {} DATA[0] {} } { 0.000ns 3.000ns } { 0.000ns 4.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}