cy62256vso.vhd.bak

用VHDL编写的CY62256VSO芯片的驱动程序.

-------CY62256VS0 INTERFACE-----------
library  IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
ENTITY  CY62256VSO  IS
PORT
(	
 GLBCLK:IN STD_LOGIC;--CLOCK
 FPGARD:IN STD_LOGIC;
 FPGAWR:IN STD_LOGIC;
 FPGACS:IN STD_LOGIC;
 FPGAADDR:IN STD_LOGIC_VECTOR(14 DOWNTO 0);
 FPGADT:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); 
 RD    :OUT STD_LOGIC;--READ SELECT SIGNAL
 WR    :OUT STD_LOGIC;--WRITE SELECT SIGNAL
 CS    :OUT STD_LOGIC;--CHIP SELCET SIGNAL 
 ADDROUT  :OUT STD_LOGIC_VECTOR(14 DOWNTO 0);--ADDREESS SIGNAL
 DATA  :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)--DATA SIGNAL 
);
END  CY62256VSO;
ARCHITECTURE BEHIVIOR OF CY62256VSO IS
     SIGNAL DAT:STD_LOGIC_VECTOR(7 DOWNTO 0);
     SIGNAL RD_WR:STD_LOGIC_VECTOR(2 DOWNTO 0):="111";
BEGIN   
     ADDROUT<=FPGAADDR;
     RD_WR<=FPGACS & FPGARD & FPGAWR; 
     CS<=RD_WR(2);
     RD<=RD_WR(1);
     WR<=RD_WR(0);
     PROCESS(GLBCLK,RD_WR)
        BEGIN                         
             IF GLBCLK'EVENT AND GLBCLK='1' AND GLBCLK'LAST_VALUE='0' THEN
                CASE RD_WR IS
                 WHEN  "001" => 
                               DATA<="ZZZZZZZZ";
                               FPGADT<=DATA;
                 WHEN  "010" =>
                               FPGADT<="ZZZZZZZZ";
                               DATA<=FPGADT;
                 WHEN OTHERS =>
                               RD_WR<="111";
                END CASE;
             END IF;
     END PROCESS;
END BEHIVIOR;