📄 cy62256vso.sim.rpt
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; |CY62256VSO|CS~reg0 ; |CY62256VSO|CS~reg0 ; dataout ;
; |CY62256VSO|FPGARD ; |CY62256VSO|FPGARD~corein ; dataout ;
; |CY62256VSO|FPGAWR ; |CY62256VSO|FPGAWR~corein ; dataout ;
; |CY62256VSO|FPGACS ; |CY62256VSO|FPGACS~corein ; dataout ;
; |CY62256VSO|FPGAADDR[0] ; |CY62256VSO|FPGAADDR[0]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[1] ; |CY62256VSO|FPGAADDR[1]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[2] ; |CY62256VSO|FPGAADDR[2]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[3] ; |CY62256VSO|FPGAADDR[3]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[4] ; |CY62256VSO|FPGAADDR[4]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[5] ; |CY62256VSO|FPGAADDR[5]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[6] ; |CY62256VSO|FPGAADDR[6]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[7] ; |CY62256VSO|FPGAADDR[7]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[8] ; |CY62256VSO|FPGAADDR[8]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[9] ; |CY62256VSO|FPGAADDR[9]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[10] ; |CY62256VSO|FPGAADDR[10]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[11] ; |CY62256VSO|FPGAADDR[11]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[12] ; |CY62256VSO|FPGAADDR[12]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[13] ; |CY62256VSO|FPGAADDR[13]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[14] ; |CY62256VSO|FPGAADDR[14]~corein ; dataout ;
; |CY62256VSO|DATA[0] ; |CY62256VSO|DATA[0]~output ; padio ;
; |CY62256VSO|DATA[1] ; |CY62256VSO|DATA[1]~output ; padio ;
; |CY62256VSO|DATA[2] ; |CY62256VSO|DATA[2]~output ; padio ;
; |CY62256VSO|DATA[3] ; |CY62256VSO|DATA[3]~output ; padio ;
; |CY62256VSO|DATA[4] ; |CY62256VSO|DATA[4]~output ; padio ;
; |CY62256VSO|DATA[5] ; |CY62256VSO|DATA[5]~output ; padio ;
; |CY62256VSO|DATA[6] ; |CY62256VSO|DATA[6]~output ; padio ;
; |CY62256VSO|DATA[7] ; |CY62256VSO|DATA[7]~output ; padio ;
; |CY62256VSO|ADDROUT[0] ; |CY62256VSO|ADDROUT[0] ; padio ;
; |CY62256VSO|ADDROUT[1] ; |CY62256VSO|ADDROUT[1] ; padio ;
; |CY62256VSO|ADDROUT[2] ; |CY62256VSO|ADDROUT[2] ; padio ;
; |CY62256VSO|ADDROUT[3] ; |CY62256VSO|ADDROUT[3] ; padio ;
; |CY62256VSO|ADDROUT[4] ; |CY62256VSO|ADDROUT[4] ; padio ;
; |CY62256VSO|ADDROUT[5] ; |CY62256VSO|ADDROUT[5] ; padio ;
; |CY62256VSO|ADDROUT[6] ; |CY62256VSO|ADDROUT[6] ; padio ;
; |CY62256VSO|ADDROUT[7] ; |CY62256VSO|ADDROUT[7] ; padio ;
; |CY62256VSO|ADDROUT[8] ; |CY62256VSO|ADDROUT[8] ; padio ;
; |CY62256VSO|ADDROUT[9] ; |CY62256VSO|ADDROUT[9] ; padio ;
; |CY62256VSO|ADDROUT[10] ; |CY62256VSO|ADDROUT[10] ; padio ;
; |CY62256VSO|ADDROUT[11] ; |CY62256VSO|ADDROUT[11] ; padio ;
; |CY62256VSO|ADDROUT[12] ; |CY62256VSO|ADDROUT[12] ; padio ;
; |CY62256VSO|ADDROUT[13] ; |CY62256VSO|ADDROUT[13] ; padio ;
; |CY62256VSO|ADDROUT[14] ; |CY62256VSO|ADDROUT[14] ; padio ;
; |CY62256VSO|RD ; |CY62256VSO|RD ; padio ;
; |CY62256VSO|CS ; |CY62256VSO|CS ; padio ;
+-----------------------------+---------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-----------------------------+---------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------------+---------------------------------+------------------+
; |CY62256VSO|FPGAADDR[0]~30 ; |CY62256VSO|FPGAADDR[0]~30 ; dataout ;
; |CY62256VSO|FPGAADDR[1]~32 ; |CY62256VSO|FPGAADDR[1]~32 ; dataout ;
; |CY62256VSO|FPGAADDR[2]~34 ; |CY62256VSO|FPGAADDR[2]~34 ; dataout ;
; |CY62256VSO|FPGAADDR[3]~36 ; |CY62256VSO|FPGAADDR[3]~36 ; dataout ;
; |CY62256VSO|FPGAADDR[4]~38 ; |CY62256VSO|FPGAADDR[4]~38 ; dataout ;
; |CY62256VSO|FPGAADDR[5]~40 ; |CY62256VSO|FPGAADDR[5]~40 ; dataout ;
; |CY62256VSO|FPGAADDR[6]~42 ; |CY62256VSO|FPGAADDR[6]~42 ; dataout ;
; |CY62256VSO|FPGAADDR[7]~44 ; |CY62256VSO|FPGAADDR[7]~44 ; dataout ;
; |CY62256VSO|FPGAADDR[8]~46 ; |CY62256VSO|FPGAADDR[8]~46 ; dataout ;
; |CY62256VSO|FPGAADDR[9]~48 ; |CY62256VSO|FPGAADDR[9]~48 ; dataout ;
; |CY62256VSO|FPGAADDR[10]~50 ; |CY62256VSO|FPGAADDR[10]~50 ; dataout ;
; |CY62256VSO|FPGAADDR[11]~52 ; |CY62256VSO|FPGAADDR[11]~52 ; dataout ;
; |CY62256VSO|FPGAADDR[12]~54 ; |CY62256VSO|FPGAADDR[12]~54 ; dataout ;
; |CY62256VSO|FPGAADDR[13]~56 ; |CY62256VSO|FPGAADDR[13]~56 ; dataout ;
; |CY62256VSO|FPGAADDR[14]~58 ; |CY62256VSO|FPGAADDR[14]~58 ; dataout ;
; |CY62256VSO|WR~reg0 ; |CY62256VSO|WR~reg0 ; dataout ;
; |CY62256VSO|RD~reg0 ; |CY62256VSO|RD~reg0 ; dataout ;
; |CY62256VSO|CS~reg0 ; |CY62256VSO|CS~reg0 ; dataout ;
; |CY62256VSO|FPGARD ; |CY62256VSO|FPGARD~corein ; dataout ;
; |CY62256VSO|FPGAWR ; |CY62256VSO|FPGAWR~corein ; dataout ;
; |CY62256VSO|FPGACS ; |CY62256VSO|FPGACS~corein ; dataout ;
; |CY62256VSO|FPGAADDR[0] ; |CY62256VSO|FPGAADDR[0]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[1] ; |CY62256VSO|FPGAADDR[1]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[2] ; |CY62256VSO|FPGAADDR[2]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[3] ; |CY62256VSO|FPGAADDR[3]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[4] ; |CY62256VSO|FPGAADDR[4]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[5] ; |CY62256VSO|FPGAADDR[5]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[6] ; |CY62256VSO|FPGAADDR[6]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[7] ; |CY62256VSO|FPGAADDR[7]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[8] ; |CY62256VSO|FPGAADDR[8]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[9] ; |CY62256VSO|FPGAADDR[9]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[10] ; |CY62256VSO|FPGAADDR[10]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[11] ; |CY62256VSO|FPGAADDR[11]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[12] ; |CY62256VSO|FPGAADDR[12]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[13] ; |CY62256VSO|FPGAADDR[13]~corein ; dataout ;
; |CY62256VSO|FPGAADDR[14] ; |CY62256VSO|FPGAADDR[14]~corein ; dataout ;
; |CY62256VSO|DATA[0] ; |CY62256VSO|DATA[0]~output ; padio ;
; |CY62256VSO|DATA[1] ; |CY62256VSO|DATA[1]~output ; padio ;
; |CY62256VSO|DATA[2] ; |CY62256VSO|DATA[2]~output ; padio ;
; |CY62256VSO|DATA[3] ; |CY62256VSO|DATA[3]~output ; padio ;
; |CY62256VSO|DATA[4] ; |CY62256VSO|DATA[4]~output ; padio ;
; |CY62256VSO|DATA[5] ; |CY62256VSO|DATA[5]~output ; padio ;
; |CY62256VSO|DATA[6] ; |CY62256VSO|DATA[6]~output ; padio ;
; |CY62256VSO|DATA[7] ; |CY62256VSO|DATA[7]~output ; padio ;
; |CY62256VSO|ADDROUT[0] ; |CY62256VSO|ADDROUT[0] ; padio ;
; |CY62256VSO|ADDROUT[1] ; |CY62256VSO|ADDROUT[1] ; padio ;
; |CY62256VSO|ADDROUT[2] ; |CY62256VSO|ADDROUT[2] ; padio ;
; |CY62256VSO|ADDROUT[3] ; |CY62256VSO|ADDROUT[3] ; padio ;
; |CY62256VSO|ADDROUT[4] ; |CY62256VSO|ADDROUT[4] ; padio ;
; |CY62256VSO|ADDROUT[5] ; |CY62256VSO|ADDROUT[5] ; padio ;
; |CY62256VSO|ADDROUT[6] ; |CY62256VSO|ADDROUT[6] ; padio ;
; |CY62256VSO|ADDROUT[7] ; |CY62256VSO|ADDROUT[7] ; padio ;
; |CY62256VSO|ADDROUT[8] ; |CY62256VSO|ADDROUT[8] ; padio ;
; |CY62256VSO|ADDROUT[9] ; |CY62256VSO|ADDROUT[9] ; padio ;
; |CY62256VSO|ADDROUT[10] ; |CY62256VSO|ADDROUT[10] ; padio ;
; |CY62256VSO|ADDROUT[11] ; |CY62256VSO|ADDROUT[11] ; padio ;
; |CY62256VSO|ADDROUT[12] ; |CY62256VSO|ADDROUT[12] ; padio ;
; |CY62256VSO|ADDROUT[13] ; |CY62256VSO|ADDROUT[13] ; padio ;
; |CY62256VSO|ADDROUT[14] ; |CY62256VSO|ADDROUT[14] ; padio ;
; |CY62256VSO|RD ; |CY62256VSO|RD ; padio ;
; |CY62256VSO|WR ; |CY62256VSO|WR ; padio ;
; |CY62256VSO|CS ; |CY62256VSO|CS ; padio ;
+-----------------------------+---------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Jan 08 17:20:23 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off CY62256VSO -c CY62256VSO
Info: Using vector source file "E:/CY62256VSO/CY62256VSO.vwf"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[0]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[1]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[2]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[3]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[4]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[5]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[6]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[7]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[8]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[9]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[10]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[11]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[12]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[13]"
Warning: Can't find signal in vector source file for input pin "|CY62256VSO|FPGAADDR[14]"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 28.74 %
Info: Number of transitions in simulation is 3910
Info: Quartus II Simulator was successful. 0 errors, 15 warnings
Info: Allocated 97 megabytes of memory during processing
Info: Processing ended: Thu Jan 08 17:20:24 2009
Info: Elapsed time: 00:00:01
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