cy62256vso.tan.summary

来自「用VHDL编写的CY62256VSO芯片的驱动程序.」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.200 ns
From           : FPGARD
To             : FPGADT[0]~reg0
From Clock     : --
To Clock       : GLBCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.700 ns
From           : FPGADT[0]~en
To             : FPGADT[7]
From Clock     : GLBCLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.100 ns
From           : FPGARD
To             : RD
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.900 ns
From           : FPGADT[7]
To             : DATA[7]~reg0
From Clock     : --
To Clock       : GLBCLK
Failed Paths   : 0

Type           : Clock Setup: 'GLBCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 116.28 MHz ( period = 8.600 ns )
From           : FPGADT[0]~reg0
To             : FPGADT[0]~reg0
From Clock     : GLBCLK
To Clock       : GLBCLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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