prev_cmp_pci.tan.qmsg

用VHDL编写的RTL8109与单片机的接口驱动程序.

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "AD\[8\]\$latch~16 " "Warning: Node \"AD\[8\]\$latch~16\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "AD\[0\]\$latch~16 " "Warning: Node \"AD\[0\]\$latch~16\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "AD\[31\]_1393~16 " "Warning: Node \"AD\[31\]_1393~16\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "AD\[24\]\$latch~16 " "Warning: Node \"AD\[24\]\$latch~16\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "P0\[0\]\$latch~16 " "Warning: Node \"P0\[0\]\$latch~16\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "P0_out\[0\]~3138 " "Warning: Node \"P0_out\[0\]~3138\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 115 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "ad_in\[24\]~301 " "Warning: Node \"ad_in\[24\]~301\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "ad_in\[0\]~289 " "Warning: Node \"ad_in\[0\]~289\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "ad_in\[8\]~293 " "Warning: Node \"ad_in\[8\]~293\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "ad_in\[16\]~297 " "Warning: Node \"ad_in\[16\]~297\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "P0_in\[0\]~173 " "Warning: Node \"P0_in\[0\]~173\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "P0\[0\]_1477~16 " "Warning: Node \"P0\[0\]_1477~16\"" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_IN " "Info: Assuming node \"CLK_IN\" is an undefined clock" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 13 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_IN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_IN register irdy_signal register C_BE\[0\]~reg0 57.47 MHz 17.4 ns Internal " "Info: Clock \"CLK_IN\" has Internal fmax of 57.47 MHz between source register \"irdy_signal\" and destination register \"C_BE\[0\]~reg0\" (period= 17.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns + Longest register register " "Info: + Longest register to register delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns irdy_signal 1 REG LC1 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'irdy_signal'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { irdy_signal } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.200 ns) 5.300 ns C_BE\[0\]~reg0 2 REG LC153 1 " "Info: 2: + IC(3.100 ns) + CELL(2.200 ns) = 5.300 ns; Loc. = LC153; Fanout = 1; REG Node = 'C_BE\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { irdy_signal C_BE[0]~reg0 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 104 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 41.51 % ) " "Info: Total cell delay = 2.200 ns ( 41.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 58.49 % ) " "Info: Total interconnect delay = 3.100 ns ( 58.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { irdy_signal C_BE[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { irdy_signal {} C_BE[0]~reg0 {} } { 0.000ns 3.100ns } { 0.000ns 2.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_IN\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK_IN 1 CLK PIN_184 48 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 48; CLK Node = 'CLK_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns C_BE\[0\]~reg0 2 REG LC153 1 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC153; Fanout = 1; REG Node = 'C_BE\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { CLK_IN C_BE[0]~reg0 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 104 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN C_BE[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} C_BE[0]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK_IN\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK_IN 1 CLK PIN_184 48 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 48; CLK Node = 'CLK_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns irdy_signal 2 REG LC1 11 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC1; Fanout = 11; REG Node = 'irdy_signal'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} irdy_signal {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN C_BE[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} C_BE[0]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} irdy_signal {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 104 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 104 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { irdy_signal C_BE[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { irdy_signal {} C_BE[0]~reg0 {} } { 0.000ns 3.100ns } { 0.000ns 2.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN C_BE[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} C_BE[0]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} irdy_signal {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "ad_out\[24\] P2\[3\] CLK_IN 19.000 ns register " "Info: tsu for register \"ad_out\[24\]\" (data pin = \"P2\[3\]\", clock pin = \"CLK_IN\") is 19.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.300 ns + Longest pin register " "Info: + Longest pin to register delay is 19.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns P2\[3\] 1 PIN PIN_24 110 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_24; Fanout = 110; PIN Node = 'P2\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P2[3] } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.800 ns) 7.300 ns cpld_cs~62 2 COMB LC34 287 " "Info: 2: + IC(3.800 ns) + CELL(2.800 ns) = 7.300 ns; Loc. = LC34; Fanout = 287; COMB Node = 'cpld_cs~62'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { P2[3] cpld_cs~62 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 14.000 ns P0_in\[0\]~173 3 COMB LOOP LC65 7 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 14.000 ns; Loc. = LC65; Fanout = 7; COMB LOOP Node = 'P0_in\[0\]~173'" { { "Info" "ITDB_PART_OF_SCC" "P0_in\[0\]~173 LC65 " "Info: Loc. = LC65; Node \"P0_in\[0\]~173\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0_in[0]~173 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0_in[0]~173 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { cpld_cs~62 P0_in[0]~173 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.200 ns) 19.300 ns ad_out\[24\] 4 REG LC44 3 " "Info: 4: + IC(3.100 ns) + CELL(2.200 ns) = 19.300 ns; Loc. = LC44; Fanout = 3; REG Node = 'ad_out\[24\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { P0_in[0]~173 ad_out[24] } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.400 ns ( 64.25 % ) " "Info: Total cell delay = 12.400 ns ( 64.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 35.75 % ) " "Info: Total interconnect delay = 6.900 ns ( 35.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "19.300 ns" { P2[3] cpld_cs~62 P0_in[0]~173 ad_out[24] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "19.300 ns" { P2[3] {} P2[3]~out {} cpld_cs~62 {} P0_in[0]~173 {} ad_out[24] {} } { 0.000ns 0.000ns 3.800ns 0.000ns 3.100ns } { 0.000ns 0.700ns 2.800ns 6.700ns 2.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_IN\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK_IN 1 CLK PIN_184 48 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 48; CLK Node = 'CLK_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns ad_out\[24\] 2 REG LC44 3 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC44; Fanout = 3; REG Node = 'ad_out\[24\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { CLK_IN ad_out[24] } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN ad_out[24] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} ad_out[24] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "19.300 ns" { P2[3] cpld_cs~62 P0_in[0]~173 ad_out[24] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "19.300 ns" { P2[3] {} P2[3]~out {} cpld_cs~62 {} P0_in[0]~173 {} ad_out[24] {} } { 0.000ns 0.000ns 3.800ns 0.000ns 3.100ns } { 0.000ns 0.700ns 2.800ns 6.700ns 2.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN ad_out[24] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} ad_out[24] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_IN IDSEL irdy_signal 10.600 ns register " "Info: tco from clock \"CLK_IN\" to destination pin \"IDSEL\" through register \"irdy_signal\" is 10.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK_IN\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns CLK_IN 1 CLK PIN_184 48 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_184; Fanout = 48; CLK Node = 'CLK_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.400 ns irdy_signal 2 REG LC1 11 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.400 ns; Loc. = LC1; Fanout = 11; REG Node = 'irdy_signal'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} irdy_signal {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns + Longest register pin " "Info: + Longest register to pin delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns irdy_signal 1 REG LC1 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 11; REG Node = 'irdy_signal'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { irdy_signal } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 169 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.800 ns) 5.900 ns IDSEL~9 2 COMB LC149 1 " "Info: 2: + IC(3.100 ns) + CELL(2.800 ns) = 5.900 ns; Loc. = LC149; Fanout = 1; COMB Node = 'IDSEL~9'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { irdy_signal IDSEL~9 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 6.900 ns IDSEL 3 PIN PIN_123 0 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 6.900 ns; Loc. = PIN_123; Fanout = 0; PIN Node = 'IDSEL'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { IDSEL~9 IDSEL } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 55.07 % ) " "Info: Total cell delay = 3.800 ns ( 55.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 44.93 % ) " "Info: Total interconnect delay = 3.100 ns ( 44.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { irdy_signal IDSEL~9 IDSEL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { irdy_signal {} IDSEL~9 {} IDSEL {} } { 0.000ns 3.100ns 0.000ns } { 0.000ns 2.800ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK_IN irdy_signal } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK_IN {} CLK_IN~out {} irdy_signal {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.800ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { irdy_signal IDSEL~9 IDSEL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { irdy_signal {} IDSEL~9 {} IDSEL {} } { 0.000ns 3.100ns 0.000ns } { 0.000ns 2.800ns 1.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "RD P0\[7\] 32.500 ns Longest " "Info: Longest tpd from source pin \"RD\" to destination pin \"P0\[7\]\" is 32.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns RD 1 PIN PIN_100 104 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_100; Fanout = 104; PIN Node = 'RD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.800 ns) 7.300 ns P0_in\[0\]~142 2 COMB LC2 147 " "Info: 2: + IC(3.800 ns) + CELL(2.800 ns) = 7.300 ns; Loc. = LC2; Fanout = 147; COMB Node = 'P0_in\[0\]~142'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.600 ns" { RD P0_in[0]~142 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 14.000 ns ad_in\[23\]~409 3 COMB LOOP LC126 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 14.000 ns; Loc. = LC126; Fanout = 4; COMB LOOP Node = 'ad_in\[23\]~409'" { { "Info" "ITDB_PART_OF_SCC" "ad_in\[23\]~409 LC126 " "Info: Loc. = LC126; Node \"ad_in\[23\]~409\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad_in[23]~409 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ad_in[23]~409 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { P0_in[0]~142 ad_in[23]~409 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 196 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.800 ns) 19.800 ns P0_out\[7\]~3076 4 COMB LC128 3 " "Info: 4: + IC(3.000 ns) + CELL(2.800 ns) = 19.800 ns; Loc. = LC128; Fanout = 3; COMB Node = 'P0_out\[7\]~3076'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { ad_in[23]~409 P0_out[7]~3076 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.800 ns) 25.600 ns P0_out\[7\]~3166 5 COMB LOOP LC82 5 " "Info: 5: + IC(0.000 ns) + CELL(5.800 ns) = 25.600 ns; Loc. = LC82; Fanout = 5; COMB LOOP Node = 'P0_out\[7\]~3166'" { { "Info" "ITDB_PART_OF_SCC" "P0_out\[7\]~3166 LC82 " "Info: Loc. = LC82; Node \"P0_out\[7\]~3166\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0_out[7]~3166 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0_out[7]~3166 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 115 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { P0_out[7]~3076 P0_out[7]~3166 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.900 ns) 31.500 ns P0\[7\]\$latch~16 6 COMB LOOP LC163 3 " "Info: 6: + IC(0.000 ns) + CELL(5.900 ns) = 31.500 ns; Loc. = LC163; Fanout = 3; COMB LOOP Node = 'P0\[7\]\$latch~16'" { { "Info" "ITDB_PART_OF_SCC" "P0\[7\]\$latch~16 LC163 " "Info: Loc. = LC163; Node \"P0\[7\]\$latch~16\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0[7]$latch~16 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "P0_out\[7\]~3166 LC82 " "Info: Loc. = LC82; Node \"P0_out\[7\]~3166\"" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0_out[7]~3166 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0[7]$latch~16 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 0 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { P0_out[7]~3166 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 115 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { P0_out[7]~3166 P0[7]$latch~16 } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 32.500 ns P0\[7\] 7 PIN PIN_117 0 " "Info: 7: + IC(0.000 ns) + CELL(1.000 ns) = 32.500 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'P0\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { P0[7]$latch~16 P0[7] } "NODE_NAME" } } { "PCI.vhd" "" { Text "E:/PCI/PCI.vhd" 179 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.700 ns ( 79.08 % ) " "Info: Total cell delay = 25.700 ns ( 79.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.800 ns ( 20.92 % ) " "Info: Total interconnect delay = 6.800 ns ( 20.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "32.500 ns" { RD P0_in[0]~142 ad_in[23]~409 P0_out[7]~3076 P0_out[7]~3166 P0[7]$latch~16 P0[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "32.500 ns" { RD {} RD~out {} P0_in[0]~142 {} ad_in[23]~409 {} P0_out[7]~3076 {} P0_out[7]~3166 {} P0[7]$latch~16 {} P0[7] {} } { 0.000ns 0.000ns 3.800ns 0.000ns 3.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.700ns 2.800ns 6.700ns 2.800ns 5.800ns 5.900ns 1.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ad_out\[24\] TRDY CLK_IN -2.300 ns register " "Info: th for register \"ad_out\[24\]\" (data pin = \"TRDY\", clock pin = \