prev_cmp_pci.qmsg

用VHDL编写的RTL8109与单片机的接口驱动程序.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 15 18:21:17 2009 " "Info: Processing started: Thu Jan 15 18:21:17 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PCI -c PCI " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PCI -c PCI" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PCI.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PCI.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PCI-BRIGE " "Info: Found design unit 1: PCI-BRIGE" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 PCI " "Info: Found entity 1: PCI" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PCI " "Info: Elaborating entity \"PCI\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "com_p2 PCI.vhd(54) " "Warning (10036): Verilog HDL or VHDL warning at PCI.vhd(54): object \"com_p2\" assigned a value but never read" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 54 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "P0_out PCI.vhd(115) " "Warning (10631): VHDL Process Statement warning at PCI.vhd(115): inferring latch(es) for signal or variable \"P0_out\", which holds its previous value in one or more paths through the process" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 115 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "P0 PCI.vhd(179) " "Warning (10631): VHDL Process Statement warning at PCI.vhd(179): inferring latch(es) for signal or variable \"P0\", which holds its previous value in one or more paths through the process" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 179 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "P0_in PCI.vhd(179) " "Warning (10631): VHDL Process Statement warning at PCI.vhd(179): inferring latch(es) for signal or variable \"P0_in\", which holds its previous value in one or more paths through the process" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 179 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "AD PCI.vhd(196) " "Warning (10631): VHDL Process Statement warning at PCI.vhd(196): inferring latch(es) for signal or variable \"AD\", which holds its previous value in one or more paths through the process" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ad_in PCI.vhd(196) " "Warning (10631): VHDL Process Statement warning at PCI.vhd(196): inferring latch(es) for signal or variable \"ad_in\", which holds its previous value in one or more paths through the process" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[0\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[0\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[1\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[1\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[2\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[2\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[3\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[3\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[4\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[4\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[5\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[5\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[6\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[6\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[7\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[7\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[8\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[8\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[9\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[9\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[10\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[10\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[11\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[11\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[12\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[12\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[13\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[13\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[14\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[14\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[15\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[15\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[16\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[16\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[17\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[17\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[18\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[18\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[19\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[19\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[20\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[20\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[21\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[21\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[22\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[22\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[23\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[23\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[24\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[24\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[25\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[25\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[26\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[26\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[27\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[27\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ad_in\[28\] PCI.vhd(196) " "Info (10041): Inferred latch for \"ad_in\[28\]\" at PCI.vhd(196)" {  } { { "PCI.vhd" "" { Text "H:/PCI/PCI.vhd" 196 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}