📄 pci.vhd.bak
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
ENTITY PCI IS
PORT
(
--与单片机端的接口
P0: INOUT STD_LOGIC_VECTOR( 7 DOWNTO 0); ----单片机P0口
P2: IN STD_LOGIC_VECTOR( 7 DOWNTO 0); ----单片机P2口
RD: IN STD_LOGIC; ----单片机 /RD信号
WR: IN STD_LOGIC; ----单片机 /WR信号
CLK_IN: IN STD_LOGIC; ----单片机时钟输出端X1
INT0: IN STD_LOGIC; ----单片机外部中断0
--与RTL8029端的接口
AD: INOUT STD_LOGIC_VECTOR( 31 DOWNTO 0); ----8029的32位数据
C_BE: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ----8029的字节使能信号
RST: OUT STD_LOGIC; ----8029复位信号
INTA: IN STD_LOGIC; ----8029中断输出信号
IRDY: OUT STD_LOGIC; ----8029 IRDY信号
TRDY: IN STD_LOGIC; ----8029 TRDY信号
FRAME: OUT STD_LOGIC; ----8029 FRAME信号
IDSEL: OUT STD_LOGIC; ----8029 IDSEL信号
CLK_OUT: OUT STD_LOGIC ----8029 CLK信号
);
END PCI;
ARCHITECTURE BRIGE OF PCI IS
signal P0_in: std_logic_vector(7 downto 0);
signal P0_out: std_logic_vector(7 downto 0);
signal ad_in: std_logic_vector(31 downto 0);
signal ad_out: std_logic_vector(31 downto 0);
signal cpld_cs: std_logic; ----选通
signal addr_reg0: std_logic; ----寄存器0地址选通
signal addr_reg1: std_logic; ----寄存器1地址选通
signal addr_reg2: std_logic; ----寄存器2地址选通
signal addr_reg3: std_logic; ----寄存器3地址选通
signal addr_reg4: std_logic; ----寄存器4地址选通
signal addr_reg5: std_logic; ----寄存器5地址选通
signal addr_reg6: std_logic; ----寄存器6地址选通
signal addr_reg7: std_logic; ----寄存器7地址选通
signal addr_reg8: std_logic; ----C/BE寄存器地址选通
signal addr_reg9: std_logic; ----8029复位控制寄存器地址选通
signal cmd_reg: std_logic_vector(3 downto 0);
signal byteenable_reg:std_logic_vector(3 downto 0);
signal frame_signal: std_logic;
signal frame_a: std_logic;
signal frame_b: std_logic;
signal irdy_signal: std_logic;
signal irdy_a: std_logic;
signal irdy_b: std_logic;
signal com_p2: std_logic;
BEGIN
CLK_OUT<=CLK_IN;
cpld_cs<= addr_reg0 or addr_reg1 or addr_reg2 or addr_reg3 or addr_reg4
or addr_reg5 or addr_reg6 or addr_reg7 or addr_reg8 or addr_reg9;
---------------------地址解码-------------------------
com_p2<=p2(7) and (not p2(6))and(not p2(5))and(not p2(4));
addr_reg0<=(not p2(3))and(not p2(2))and(not p2(1))and(not p2(0)) ;
addr_reg1<=(not p2(3))and(not p2(2))and(not p2(1))and( p2(0)) ;
addr_reg2<=(not p2(3))and(not p2(2))and( p2(1))and(not p2(0)) ;
addr_reg3<=(not p2(3))and(not p2(2))and( p2(1))and( p2(0)) ;
addr_reg4<=(not p2(3))and( p2(2))and(not p2(1))and(not p2(0)) ;
addr_reg5<=(not p2(3))and( p2(2))and(not p2(1))and( p2(0)) ;
addr_reg6<=(not p2(3))and( p2(2))and( p2(1))and(not p2(0)) ;
addr_reg7<=(not p2(3))and( p2(2))and( p2(1))and( p2(0)) ;
addr_reg8<=( p2(3))and(not p2(2))and(not p2(1))and(not p2(0)) ;
addr_reg9<=( p2(3))and(not p2(2))and(not p2(1))and( p2(0)) ;
-------------------------------------------------
-----------------复位信号生成----------------
process(clk_in)
begin
if(clk_in'event and clk_in='1')then
if(addr_reg9='1')then
if(wr='0')then
rst<=p0(0);
end if;
end if;
end if;
end process;
---------------------------------------------
----命令与字节使能寄存器-----------------------------
process(clk_in)
begin
if(clk_in'event and clk_in='1')then
if(addr_reg8='1')then
if(wr='0')then
cmd_reg <=p0(7 downto 4); --高4位为命令
byteenable_reg<=p0(3 downto 0); --低4位为字节使能
end if;
end if;
end if;
end process;
process(clk_in,frame_signal)
begin
if(clk_in'event and clk_in='1')then
if(frame_signal='0')then
C_BE<=cmd_reg;
else
C_BE<=byteenable_reg;
end if;
end if;
end process;
---------------------------------------------
-----------------读-----------------------------
process(rd, TRDY ,addr_reg0,addr_reg1,addr_reg2,addr_reg3,ad_in)
begin
if(rd='0' and TRDY='0')then
if (addr_reg0='1')then
p0_out<=ad_in(7 downto 0);
elsif(addr_reg1='1')then
p0_out<=ad_in(15 downto 8);
elsif(addr_reg2='1')then
p0_out<=ad_in(23 downto 16);
elsif(addr_reg3='1')then
p0_out<=ad_in(31 downto 24);
end if;
end if;
end process;
----------------------------------------------
-----------------写-----------------------------
process(clk_in,wr, TRDY ,addr_reg4,addr_reg5,addr_reg6,addr_reg7,p0_in)
begin
if(clk_in'event and clk_in='1')then
if(wr='0' and TRDY='0')then
if (addr_reg4='1')then
ad_out(7 downto 0)<=p0_in;
elsif(addr_reg5='1')then
ad_out(15 downto 8)<=p0_in;
elsif(addr_reg6='1')then
ad_out(23 downto 16)<=p0_in;
elsif(addr_reg7='1')then
ad_out(31 downto 24)<=p0_in;
end if;
end if;
end if;
end process;
----------------------------------------------
-----------------产生frame、idsel信号-------------------------------
process(clk_in,frame_a)
begin
frame_b<=not frame_a;
if(clk_in'event and clk_in='0')then
frame_a<=addr_reg8;
frame_signal<=addr_reg8 and frame_b;
end if;
end process;
FRAME <= not frame_signal;
IDSEL <= cmd_reg(3) and frame_signal;
--------------------------------------------------------------------
----------------IRDY信号的产生----------------------
process(clk_in,irdy_a)
begin
irdy_b<=not irdy_a;
if(clk_in'event and clk_in='0')then
irdy_a<= addr_reg8;
irdy_signal<= addr_reg8 and irdy_b;
end if;
end process;
IRDY<= irdy_signal;
----------------------------------------------------
----------------------P0双向总线----------------------
process(cpld_cs,rd,wr,p0,p0_out)
begin
if(cpld_cs='0' )then
p0<="ZZZZZZZZ";
else
if(wr='1' and rd='0')then --单片机读
p0<=p0_out;
p0_in<=p0;
elsif(wr='0' and rd='1')then --单片机写
p0<="ZZZZZZZZ";
p0_in<=p0;
end if;
end if;
end process;
-------------------------------------------------------
----------------------AD双向总线----------------------
process(cpld_cs,rd,wr,ad,ad_out)
begin
if(cpld_cs='0' )then
ad<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
else
if(wr='1' and rd='0')then --单片机读
ad<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
ad_in<=ad;
elsif(wr='0' and rd='1')then --单片机写
ad<=ad_out;
ad_in<=ad;
end if;
end if;
end process;
-------------------------------------------------------
END BRIGE;⌨️ 快捷键说明
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