pci.fit.rpt
来自「用VHDL编写的RTL8109与单片机的接口驱动程序.」· RPT 代码 · 共 621 行 · 第 1/5 页
RPT
621 行
; P0_out[0]~3062sexpand0 ; 7 ;
; irdy_signal ; 7 ;
; process8~26 ; 5 ;
; process7~16 ; 5 ;
; process8~25 ; 5 ;
; process7~15 ; 5 ;
; P0_in[7]~201 ; 5 ;
; P0_in[6]~197 ; 5 ;
; P0_in[5]~193 ; 5 ;
; P0_in[4]~189 ; 5 ;
; P0_in[3]~185 ; 5 ;
; P0_in[2]~181 ; 5 ;
; P0_in[1]~177 ; 5 ;
; P0_in[0]~173 ; 5 ;
; process8~29 ; 4 ;
; process7~19 ; 4 ;
; process8~28 ; 4 ;
; process7~18 ; 4 ;
; process8~27 ; 4 ;
; process7~17 ; 4 ;
; process8~24 ; 4 ;
; process7~12sexpand0 ; 4 ;
; process8~21sexpand0 ; 4 ;
; process8~30 ; 3 ;
; process7~21 ; 3 ;
; process7~20 ; 3 ;
; P0[0]~15 ; 3 ;
; P0[7]~8 ; 2 ;
; P0[6]~9 ; 2 ;
; P0[5]~10 ; 2 ;
; P0[4]~11 ; 2 ;
; P0[3]~12 ; 2 ;
; P0[2]~13 ; 2 ;
; P0[1]~14 ; 2 ;
; cmd_reg[3] ; 2 ;
; P0[7]$latch~16 ; 2 ;
; P0[6]$latch~16 ; 2 ;
; P0[5]$latch~16 ; 2 ;
; P0[4]$latch~16 ; 2 ;
+------------------------+---------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; Output enables ; 2 / 10 ( 20 % ) ;
; PIA buffers ; 271 / 1,152 ( 24 % ) ;
; PIAs ; 271 / 1,152 ( 24 % ) ;
+----------------------------+----------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+------------------------------+
; LAB External Interconnects (Average = 8.47) ; Number of LABs (Total = 11) ;
+----------------------------------------------+------------------------------+
; 0 - 2 ; 21 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 2 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 2 ;
; 27 - 29 ; 5 ;
; 30 - 32 ; 2 ;
+----------------------------------------------+------------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+------------------------------+
; Number of Macrocells (Average = 4.69) ; Number of LABs (Total = 11) ;
+----------------------------------------+------------------------------+
; 0 ; 21 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 8 ;
+----------------------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 1.31) ; Number of LABs (Total = 9) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 23 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 7 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC2 ; WR, RD ; P0[0]_1477~16, P0[0]$latch~16, P0[1]$latch~16, P0[2]$latch~16, P0[3]$latch~16, P0[4]$latch~16, P0[5]$latch~16, P0[6]$latch~16, P0[7]$latch~16, P0_in[0]~173, P0_in[1]~177, P0_in[2]~181, P0_in[3]~185, P0_in[4]~189, P0_in[5]~193, P0_in[6]~197, P0_in[7]~201, ad_in[0]~289, ad_in[8]~293, ad_in[16]~297, ad_in[24]~301, ad_in[1]~305, ad_in[9]~309, ad_in[17]~313, ad_in[25]~317, ad_in[2]~321, ad_in[10]~325, ad_in[18]~329, ad_in[26]~333, ad_in[3]~337, ad_in[11]~341, ad_in[19]~345, ad_in[27]~349, ad_in[4]~353, ad_in[12]~357, ad_in[20]~361, ad_in[28]~365, ad_in[5]~369, ad_in[13]~373, ad_in[21]~377, ad_in[29]~381, ad_in[6]~385, ad_in[14]~389, ad_in[22]~393, ad_in[30]~397, ad_in[7]~401, ad_in[15]~405, ad_in[23]~409, ad_in[31]~413 ;
; A ; LC11 ; ad_in[0]~289, ad_in[8]~293, ad_in[16]~297, ad_in[24]~301, P2[1], P2[2], P2[0], P2[3], addr_reg0~25sexpand1, addr_reg1~22sexpand0, addr_reg2~29sexpand0 ; P0_out[0]~3138 ;
; A ; LC8 ; CLK_IN, P0[2], WR, P2[0], P2[3], P2[1], P2[2] ; C_BE[2]~reg0 ;
; A ; LC5 ; CLK_IN, P0[1], WR, P2[0], P2[3], P2[1], P2[2] ; C_BE[1]~reg0
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