📄 pci.map.rpt
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; P0_out[7] ; P0_out[0]~6 ; yes ;
; ad_in[0] ; ad_in[1]~1 ; yes ;
; ad_in[8] ; ad_in[1]~1 ; yes ;
; ad_in[24] ; ad_in[1]~1 ; yes ;
; ad_in[16] ; ad_in[1]~1 ; yes ;
; ad_in[1] ; ad_in[1]~1 ; yes ;
; ad_in[9] ; ad_in[1]~1 ; yes ;
; ad_in[25] ; ad_in[1]~1 ; yes ;
; ad_in[17] ; ad_in[1]~1 ; yes ;
; ad_in[2] ; ad_in[1]~1 ; yes ;
; ad_in[10] ; ad_in[1]~1 ; yes ;
; ad_in[26] ; ad_in[1]~1 ; yes ;
; ad_in[18] ; ad_in[1]~1 ; yes ;
; ad_in[3] ; ad_in[1]~1 ; yes ;
; ad_in[11] ; ad_in[1]~1 ; yes ;
; ad_in[27] ; ad_in[1]~1 ; yes ;
; ad_in[19] ; ad_in[1]~1 ; yes ;
; ad_in[4] ; ad_in[1]~1 ; yes ;
; ad_in[12] ; ad_in[1]~1 ; yes ;
; ad_in[28] ; ad_in[1]~1 ; yes ;
; ad_in[20] ; ad_in[1]~1 ; yes ;
; ad_in[5] ; ad_in[1]~1 ; yes ;
; ad_in[13] ; ad_in[1]~1 ; yes ;
; ad_in[29] ; ad_in[1]~1 ; yes ;
; ad_in[21] ; ad_in[1]~1 ; yes ;
; ad_in[6] ; ad_in[1]~1 ; yes ;
; ad_in[14] ; ad_in[1]~1 ; yes ;
; ad_in[30] ; ad_in[1]~1 ; yes ;
; ad_in[22] ; ad_in[1]~1 ; yes ;
; ad_in[7] ; ad_in[1]~1 ; yes ;
; ad_in[15] ; ad_in[1]~1 ; yes ;
; ad_in[31] ; ad_in[1]~1 ; yes ;
; ad_in[23] ; ad_in[1]~1 ; yes ;
; P0_in[0] ; ad_in[1]~1 ; yes ;
; P0_in[1] ; ad_in[1]~1 ; yes ;
; P0_in[2] ; ad_in[1]~1 ; yes ;
; P0_in[3] ; ad_in[1]~1 ; yes ;
; P0_in[4] ; ad_in[1]~1 ; yes ;
; P0_in[5] ; ad_in[1]~1 ; yes ;
; P0_in[6] ; ad_in[1]~1 ; yes ;
; P0_in[7] ; ad_in[1]~1 ; yes ;
; Number of user-specified and inferred latches = 90 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+-----------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+-------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+-------------------------+
; frame_a ; Merged with irdy_a ;
; frame_signal ; Merged with irdy_signal ;
; Total Number of Removed Registers = 2 ; ;
+---------------------------------------+-------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Jan 15 18:21:17 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PCI -c PCI
Info: Found 2 design units, including 1 entities, in source file PCI.vhd
Info: Found design unit 1: PCI-BRIGE
Info: Found entity 1: PCI
Info: Elaborating entity "PCI" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at PCI.vhd(54): object "com_p2" assigned a value but never read
Warning (10631): VHDL Process Statement warning at PCI.vhd(115): inferring latch(es) for signal or variable "P0_out", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at PCI.vhd(179): inferring latch(es) for signal or variable "P0", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at PCI.vhd(179): inferring latch(es) for signal or variable "P0_in", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at PCI.vhd(196): inferring latch(es) for signal or variable "AD", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at PCI.vhd(196): inferring latch(es) for signal or variable "ad_in", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "ad_in[0]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[1]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[2]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[3]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[4]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[5]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[6]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[7]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[8]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[9]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[10]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[11]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[12]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[13]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[14]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[15]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[16]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[17]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[18]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[19]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[20]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[21]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[22]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[23]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[24]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[25]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[26]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[27]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[28]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[29]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[30]" at PCI.vhd(196)
Info (10041): Inferred latch for "ad_in[31]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[0]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[1]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[2]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[3]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[4]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[5]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[6]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[7]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[8]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[9]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[10]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[11]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[12]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[13]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[14]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[15]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[16]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[17]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[18]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[19]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[20]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[21]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[22]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[23]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[24]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[25]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[26]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[27]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[28]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[29]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[30]" at PCI.vhd(196)
Info (10041): Inferred latch for "AD[31]" at PCI.vhd(196)
Info (10041): Inferred latch for "P0_in[0]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[1]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[2]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[3]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[4]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[5]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[6]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_in[7]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[0]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[1]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[2]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[3]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[4]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[5]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[6]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0[7]" at PCI.vhd(179)
Info (10041): Inferred latch for "P0_out[0]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[1]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[2]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[3]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[4]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[5]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[6]" at PCI.vhd(115)
Info (10041): Inferred latch for "P0_out[7]" at PCI.vhd(115)
Info: Duplicate registers merged to single register
Info: Duplicate register "frame_a" merged to single register "irdy_a"
Info: Duplicate registers merged to single register
Info: Duplicate register "frame_signal" merged to single register "irdy_signal"
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "CLK_IN" to global clock signal
Warning: Design contains 6 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "P2[4]"
Warning (15610): No output dependent on input pin "P2[5]"
Warning (15610): No output dependent on input pin "P2[6]"
Warning (15610): No output dependent on input pin "P2[7]"
Warning (15610): No output dependent on input pin "INT0"
Warning (15610): No output dependent on input pin "INTA"
Info: Implemented 219 device resources after synthesis - the final resource count might be different
Info: Implemented 14 input pins
Info: Implemented 9 output pins
Info: Implemented 40 bidirectional pins
Info: Implemented 150 macrocells
Info: Implemented 6 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
Info: Allocated 159 megabytes of memory during processing
Info: Processing ended: Thu Jan 15 18:21:20 2009
Info: Elapsed time: 00:00:03
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