adc.vhd

vhdl实现对模数转换芯片adc0832的控制,程序采用的是状态编码输出.

library ieee;
use ieee.std_logic_1164.all;

entity adc is
port(clk,eoc:in std_logic;
     ale,start,oe,addr:out std_logic;
     input  :in  std_logic_vector(7 downto 0);
     display:out std_logic_vector(7 downto 0));
end adc;

architecture ep1k30 of adc is
type statetype is (s1,s2,s3,s4,s5,s6,s7);
signal lock:std_logic;
signal store:std_logic_vector(7 downto 0);
signal pre_state,next_state : statetype :=s1;
begin
addr   <='1';
display<= store;
    process(pre_state,eoc)
        begin
        case pre_state is
        when s1 =>  start<='0';
                    oe   <='0';
                    ale  <='0';
                    lock <='0';
                    next_state<=s2;
        when s2 =>  start<='0';
                    oe   <='0';
                    ale  <='1';
                    lock <='0';
                    next_state<=s3;
        when s3 =>  start<='1';
                    oe   <='0';
                    ale  <='1';
                    lock <='0';
                    next_state<=s4;
        when s4 =>  start<='1';
                    oe   <='0';
                    ale  <='1';
                    lock <='0';                    
                    if eoc = '0' then
                    next_state<=s5;
                    else next_state<=s4;
                    end if;
        when s5 =>  start<='0';
                    ale  <='0';
                    lock <='0';
                    oe   <='0';
                    if eoc = '1' then
                    next_state<=s6;
                    else next_state<=s5;
                    end if;                   
        when s6 =>  start<='0';
                    ale  <='0';
                    lock <='1';
                    oe   <='1';
                    next_state<=s7;
        when s7 =>  start<='0';
                    ale  <='0';
                    lock <='1';
                    oe   <='1';
                    next_state<=s1;
        when others => 
                    start<='0';
                    oe   <='0';
                    ale  <='0';
                    lock <='0';
                    next_state<=s1;
        end case;
    end process;
    process(clk)
        begin
        if rising_edge(clk)
        then pre_state <= next_state;     
        end if;
    end process;
    process(lock)
        begin
        if lock = '1' then
        store<=input;
        end if;
    end process;
end ep1k30;