txd.vhd

用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity txd is
port (reset,clk16x,wrn : in std_logic ;
	  din : in std_logic_vector(7 downto 0) ;--input parallel data 
	  tbre : out std_logic ;	--receive buffer flag
	  tsre : out std_logic ;  --send flag
	  sdo : out std_logic );  --serial data out
end txd ;

architecture v1 of txd is
signal clk1x_enable : std_logic ;
signal tsr : std_logic_vector (7 downto 0) ;
signal tbr : std_logic_vector (7 downto 0) ;
signal parity : std_logic ;
signal clkdiv : std_logic_vector(3 downto 0) ; --用来控制数据采样时钟的
signal clk1x : std_logic ;
signal no_bits_sent : std_logic_vector(3 downto 0) ;
signal wrn1 : std_logic ;
signal wrn2 : std_logic ;
begin	
	process (reset,clk16x) --对wrn进行脉宽处理，以防接收数据错误
	begin
	if reset = '0' then
		wrn1 <= '1' ;
		wrn2 <= '1' ;
	elsif clk16x'event and clk16x = '1' then
		wrn2 <= wrn1 ;
		wrn1 <= wrn ;
	end if ;
	end process ;
	process (reset,clk16x) --对clk1x_enable进行控制
	begin
	if reset = '0' then
		clk1x_enable <= '0' ;
		tbre <= '1' ;
	elsif clk16x'event and clk16x = '1' then
		if wrn1 = '1' and wrn2 = '0' then	-------------
			tbre <= '0' ;
			clk1x_enable <= '1' ;
		elsif no_bits_sent = "0010" then
			tbre <= '1' ;
		elsif no_bits_sent = "1100" then
			clk1x_enable <= '0' ;
		end if ;
	end if ;
	end process ;
	
	process (reset,wrn) --接收数据至tbr
	begin
	if reset = '0' then
		tbr <= (others => '0') ;
	elsif wrn'event and wrn = '1' then	---------
		tbr <= din ;
	end if ;
	end process ;
	
	process (reset,clk16x,clk1x_enable)
	begin
	if reset = '0' then
		clkdiv <= "0000" ;
	elsif clk16x'event and clk16x = '1' then
		if clk1x_enable = '1' then
			clkdiv <= clkdiv + "0001" ;
		end if ;
	end if ;
	end process ;

	clk1x <= clkdiv(3) ; --产生clk1x时钟
	
	process (reset,clk1x,no_bits_sent,tbr)
	begin
	if reset = '0' then
		sdo <= '1' ;
		tsre <= '1' ;
		tsr <= "00000000" ;
		parity <= '1' ;
	elsif clk1x'event and clk1x = '1' then
		if no_bits_sent = "0001" then
			tsr <= tbr ; --发送缓冲器tbr数据进入发送移位寄存器tsr
			tsre <= '0' ; --发送移位寄存器空标志置“0”
		elsif no_bits_sent = "0010" then
			sdo <= '0' ; --发送起始位信号“0”
		elsif no_bits_sent >= "0011" and no_bits_sent <= "1010" then
			tsr <= '0' &  tsr(7 downto 1); --
			sdo <= tsr(0) ;
			parity <= parity xor tsr(7) ; --数据位中的1校验
		elsif no_bits_sent = "1011" then
			sdo <= '1';	 --stop bit
			tsre <= '1';
		end if ;
	end if ;
	end process ;
	
	process (reset,clk1x,clk1x_enable) --产生发送字符长度和发送次序计数器
	begin
	if reset = '0' or clk1x_enable = '0' then
		no_bits_sent <= "0000" ;
	elsif clk1x'event and clk1x = '0' then
		if clk1x_enable = '1' then
			no_bits_sent <= no_bits_sent + "0001" ;
		end if ;
	end if ;
	end process ;
	end ;