rxd.vhd

用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity rxd is
port (reset,clk16x,rxd : in std_logic ;
	  rbr : out std_logic_vector (7 downto 0) ;
	  data_ready : out std_logic ;
	  framing_error : out std_logic ) ;
end rxd ;

architecture v1 of rxd is
signal rxd1 : std_logic ;
signal rxd2 : std_logic ;
signal clk1x_enable : std_logic ;
signal clkdiv : std_logic_vector(3 downto 0) ; 
signal rsr : std_logic_vector(7 downto 0) ;
signal no_bits_rcvd : std_logic_vector(3 downto 0) ;
signal clk1x : std_logic ;
begin
	--DFFE
	process (reset,clk16x)
	begin
	if reset = '0' then
		rxd1 <= '1' ;
		rxd2 <= '1' ;
	elsif clk16x'event and clk16x = '1' then
		rxd2 <= rxd1 ;
		rxd1 <= rxd ;
	end if ;
	end process ;
	
	process (reset,clk16x,rxd1,rxd2,no_bits_rcvd,clkdiv)
	begin
	if reset = '0' or (no_bits_rcvd = "1001" and clkdiv = "1000") then
		clk1x_enable <= '0' ;
	elsif clk16x'event and clk16x = '1' then
		if rxd1 = '0' and rxd2 = '1' then
			clk1x_enable <= '1' ;
		end if ;
	end if ;
	end process ;
	
	process (reset,clk16x,clkdiv)
	begin
	if reset = '0' then
		data_ready <= '0' ;
	elsif clk16x'event and clk16x = '1' then
		if no_bits_rcvd = "1001" then	--to be sure data is move to rbr
			data_ready <= '1' ;
		else data_ready <= '0';
		end if ;
	end if ;
	end process ;
	
	process (reset,clk16x,clk1x_enable,no_bits_rcvd)
	begin
	if reset = '0' then
		clkdiv <= "1000" ;
	elsif clk16x'event and clk16x = '1' then
		if clk1x_enable = '1' then
			clkdiv <= clkdiv + '1' ;
		end if ;
	end if ;
	end process ;
	
	clk1x <= clkdiv(3) ;
	
	process (clk1x,reset)
	begin
	if reset = '0' then
		rsr <= "00000000" ;
		rbr <= "00000000" ;
		framing_error <= '0' ;
	elsif clk1x'event and clk1x = '1' then
		if no_bits_rcvd >= "0001" and no_bits_rcvd <= "1000" then 
			--- 数据帧数据由接收串行数据端移位入接收移位寄存器
			rsr(7) <= rxd2 ;
			rsr(6 downto 0) <= rsr(7 downto 1) ;
		elsif no_bits_rcvd = "1001" then
			rbr <= rsr;
			if rxd2 = '0' then
				framing_error <= '1' ;	--the last bit must be '1'
			end if;						--one start bit , eight data bits , one stop bit
		--elsif no_bits_rcvd = "1010" then
		--	rbr <= rsr ; --接收移位寄存器数据进入接收缓冲器
		end if ;
	end if ;
	end process ;
	
	process (reset,clk1x,clk1x_enable,no_bits_rcvd,clkdiv)
	begin
	if reset = '0' or (no_bits_rcvd = "1001" and clk1x_enable = '0' and clkdiv = "1000") then
		no_bits_rcvd <= "0000" ;
	elsif clk1x'event and clk1x = '0' then
		if clk1x_enable = '1' then
			no_bits_rcvd <= no_bits_rcvd + '1' ;
		end if ;
	end if ;
	end process ;
end ;