uart.vhd

用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity uart is
port(sysclk,reset,rxdin:in std_logic;
	 data:out std_logic_vector(7 downto 0);
	 tbre,tsre,ready:out std_logic;
	 txdo:out std_logic);
end uart;

architecture top of uart is

component txd
port (reset,clk16x,wrn : in std_logic ;
	  din : in std_logic_vector(7 downto 0) ;--input parallel data 
	  tbre : out std_logic ;	--receive buffer flag
	  tsre : out std_logic ;  --send flag
	  sdo : out std_logic );  --serial data out
end component;

component rxd
port (reset,clk16x,rxd : in std_logic ;
	  rbr : out std_logic_vector (7 downto 0) ;
	  data_ready : out std_logic ;
	  framing_error : out std_logic );
end component;

signal data_tmp: std_logic_vector (7 downto 0) ;
signal rd,rdn:std_logic;
signal clk16x:std_logic;
signal sysclkdiv:std_logic_vector( 3 downto 0);
begin
	process (reset,sysclk)		--10.84444
	begin						--band 115200
	if reset = '0' then
		sysclkdiv <= "0000";
	elsif sysclk'event and sysclk = '1' then
		sysclkdiv <= sysclkdiv + '1';
		if sysclkdiv = "1010" then
			sysclkdiv <= "0000";
			clk16x <= '0';
		elsif sysclkdiv >= "0101" then
			clk16x <= '1';
		end if;
	end if;
	end process;
	
	U1:txd port map(reset=>reset,clk16x=>clk16x,wrn=>rd,din=>data_tmp,sdo=>txdo,tbre=>tbre,tsre=>tsre);
	U2:rxd port map(reset=>reset,clk16x=>clk16x,data_ready=>rdn,rxd=>rxdin,rbr=>data_tmp);
	data<=data_tmp;
	rd<= not rdn;
	ready<=rd;
end top;