bijiaoqi.tan.rpt

4位电子智能密码锁

; N/A   ; None         ; 4.600 ns   ; INB[0] ; OPEN_LOCK$latch ; EN       ;
+-------+--------------+------------+--------+-----------------+----------+


+------------------------------------------------------------------------------+
; tco                                                                          ;
+-------+--------------+------------+-----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To        ; From Clock ;
+-------+--------------+------------+-----------------+-----------+------------+
; N/A   ; None         ; 13.500 ns  ; OPEN_LOCK$latch ; OPEN_LOCK ; EN         ;
; N/A   ; None         ; 13.300 ns  ; OPEN_LOCK$latch ; OPEN_LOCK ; ZS         ;
+-------+--------------+------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+--------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To              ; To Clock ;
+---------------+-------------+-----------+--------+-----------------+----------+
; N/A           ; None        ; -1.100 ns ; INA[0] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -1.100 ns ; INB[0] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -1.200 ns ; INB[2] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -1.300 ns ; INA[0] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -1.300 ns ; INB[0] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -1.400 ns ; INB[2] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -4.600 ns ; INB[3] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -4.800 ns ; INB[3] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -5.000 ns ; INA[3] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -5.200 ns ; INA[3] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -5.200 ns ; INA[1] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -5.200 ns ; INB[1] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -5.400 ns ; INA[1] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -5.400 ns ; INB[1] ; OPEN_LOCK$latch ; ZS       ;
; N/A           ; None        ; -6.000 ns ; INA[2] ; OPEN_LOCK$latch ; EN       ;
; N/A           ; None        ; -6.200 ns ; INA[2] ; OPEN_LOCK$latch ; ZS       ;
+---------------+-------------+-----------+--------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Jul 15 20:11:02 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BIJIAOQI -c BIJIAOQI
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "OPEN_LOCK$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "ZS" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "EN" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "process0~0" as buffer
Info: tsu for register "OPEN_LOCK$latch" (data pin = "INA[2]", clock pin = "ZS") is 9.700 ns
    Info: + Longest pin to register delay is 11.700 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_23; Fanout = 1; PIN Node = 'INA[2]'
        Info: 2: + IC(2.400 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC2_D16; Fanout = 1; COMB Node = 'Equal0~34'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 9.700 ns; Loc. = LC3_D16; Fanout = 1; COMB Node = 'Equal0~31'
        Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 11.700 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK$latch'
        Info: Total cell delay = 9.000 ns ( 76.92 % )
        Info: Total interconnect delay = 2.700 ns ( 23.08 % )
    Info: + Micro setup delay of destination is 3.500 ns
    Info: - Shortest clock path from clock "ZS" to destination register is 5.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 1; CLK Node = 'ZS'
        Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC4_D16; Fanout = 1; COMB Node = 'process0~0'
        Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.500 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK$latch'
        Info: Total cell delay = 5.000 ns ( 90.91 % )
        Info: Total interconnect delay = 0.500 ns ( 9.09 % )
Info: tco from clock "EN" to destination pin "OPEN_LOCK" through register "OPEN_LOCK$latch" is 13.500 ns
    Info: + Longest clock path from clock "EN" to source register is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; CLK Node = 'EN'
        Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC4_D16; Fanout = 1; COMB Node = 'process0~0'
        Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.700 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK$latch'
        Info: Total cell delay = 5.200 ns ( 91.23 % )
        Info: Total interconnect delay = 0.500 ns ( 8.77 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 7.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK$latch'
        Info: 2: + IC(1.500 ns) + CELL(6.300 ns) = 7.800 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'OPEN_LOCK'
        Info: Total cell delay = 6.300 ns ( 80.77 % )
        Info: Total interconnect delay = 1.500 ns ( 19.23 % )
Info: th for register "OPEN_LOCK$latch" (data pin = "INA[0]", clock pin = "EN") is -1.100 ns
    Info: + Longest clock path from clock "EN" to destination register is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; CLK Node = 'EN'
        Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC4_D16; Fanout = 1; COMB Node = 'process0~0'
        Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.700 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK$latch'
        Info: Total cell delay = 5.200 ns ( 91.23 % )
        Info: Total interconnect delay = 0.500 ns ( 8.77 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 6.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 1; PIN Node = 'INA[0]'
        Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC2_D16; Fanout = 1; COMB Node = 'Equal0~34'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 4.800 ns; Loc. = LC3_D16; Fanout = 1; COMB Node = 'Equal0~31'
        Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 6.800 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK$latch'
        Info: Total cell delay = 6.300 ns ( 92.65 % )
        Info: Total interconnect delay = 0.500 ns ( 7.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 107 megabytes of memory during processing
    Info: Processing ended: Sun Jul 15 20:11:03 2007
    Info: Elapsed time: 00:00:01