📄 first_press.tan.rpt
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Classic Timing Analyzer report for FIRST_PRESS
Fri Feb 16 09:29:57 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. th
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-----------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------+-------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.500 ns ; KEY_IN[1] ; KEY_BUFF[1] ; -- ; RST ; 0 ;
; Worst-case th ; N/A ; None ; -0.200 ns ; KEY_IN[1] ; KEY_BUFF[1] ; -- ; RST ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-----------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1K30TC144-3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; RST ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-----------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-----------+-------------+----------+
; N/A ; None ; 3.500 ns ; KEY_IN[2] ; KEY_BUFF[2] ; RST ;
; N/A ; None ; 3.500 ns ; KEY_IN[0] ; KEY_BUFF[0] ; RST ;
; N/A ; None ; 3.500 ns ; KEY_IN[3] ; KEY_BUFF[3] ; RST ;
; N/A ; None ; 3.500 ns ; KEY_IN[1] ; KEY_BUFF[1] ; RST ;
+-------+--------------+------------+-----------+-------------+----------+
+------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-----------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-----------+-------------+----------+
; N/A ; None ; -0.200 ns ; KEY_IN[2] ; KEY_BUFF[2] ; RST ;
; N/A ; None ; -0.200 ns ; KEY_IN[0] ; KEY_BUFF[0] ; RST ;
; N/A ; None ; -0.200 ns ; KEY_IN[3] ; KEY_BUFF[3] ; RST ;
; N/A ; None ; -0.200 ns ; KEY_IN[1] ; KEY_BUFF[1] ; RST ;
+---------------+-------------+-----------+-----------+-------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Feb 16 09:29:56 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FIRST_PRESS -c FIRST_PRESS
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "TOUT$latch" is a latch
Warning: Node "KEY_CNT" is a latch
Warning: Node "KEY_BUFF[3]" is a latch
Warning: Node "KEY_BUFF[1]" is a latch
Warning: Node "KEY_BUFF[2]" is a latch
Warning: Node "KEY_BUFF[0]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "RST" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "KEY_CNT" as buffer
Info: tsu for register "KEY_BUFF[2]" (data pin = "KEY_IN[2]", clock pin = "RST") is 3.500 ns
Info: + Longest pin to register delay is 3.800 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 2; PIN Node = 'KEY_IN[2]'
Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF[2]'
Info: Total cell delay = 3.600 ns ( 94.74 % )
Info: Total interconnect delay = 0.200 ns ( 5.26 % )
Info: + Micro setup delay of destination is 3.300 ns
Info: - Shortest clock path from clock "RST" to destination register is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 6; CLK Node = 'RST'
Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF[2]'
Info: Total cell delay = 3.400 ns ( 94.44 % )
Info: Total interconnect delay = 0.200 ns ( 5.56 % )
Info: th for register "KEY_BUFF[2]" (data pin = "KEY_IN[2]", clock pin = "RST") is -0.200 ns
Info: + Longest clock path from clock "RST" to destination register is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 6; CLK Node = 'RST'
Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF[2]'
Info: Total cell delay = 3.400 ns ( 94.44 % )
Info: Total interconnect delay = 0.200 ns ( 5.56 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: - Shortest pin to register delay is 3.800 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 2; PIN Node = 'KEY_IN[2]'
Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF[2]'
Info: Total cell delay = 3.600 ns ( 94.74 % )
Info: Total interconnect delay = 0.200 ns ( 5.26 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 9 warnings
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Fri Feb 16 09:29:57 2007
Info: Elapsed time: 00:00:01
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