dp_test.fit.qmsg

本程序是用VHDL语言编写的

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.779 ns register pin " "Info: Estimated most critical path is register to pin delay of 6.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns A_moto\[3\] 1 REG LAB_X16_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y7; Fanout = 1; REG Node = 'A_moto\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { A_moto[3] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.914 ns) 1.436 ns A_moto_dir~29 2 COMB LAB_X16_Y7 34 " "Info: 2: + IC(0.522 ns) + CELL(0.914 ns) = 1.436 ns; Loc. = LAB_X16_Y7; Fanout = 34; COMB Node = 'A_moto_dir~29'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "1.436 ns" { A_moto[3] A_moto_dir~29 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.519 ns) + CELL(0.740 ns) 2.695 ns A_moto_dir~30 3 COMB LAB_X16_Y7 1 " "Info: 3: + IC(0.519 ns) + CELL(0.740 ns) = 2.695 ns; Loc. = LAB_X16_Y7; Fanout = 1; COMB Node = 'A_moto_dir~30'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "1.259 ns" { A_moto_dir~29 A_moto_dir~30 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.762 ns) + CELL(2.322 ns) 6.779 ns Moto_A_dir 4 PIN PIN_108 0 " "Info: 4: + IC(1.762 ns) + CELL(2.322 ns) = 6.779 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'Moto_A_dir'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.084 ns" { A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.976 ns ( 58.65 % ) " "Info: Total cell delay = 3.976 ns ( 58.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.803 ns ( 41.35 % ) " "Info: Total interconnect delay = 2.803 ns ( 41.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.779 ns" { A_moto[3] A_moto_dir~29 A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 15 " "Info: Average interconnect usage is 10% of the available device resources. Peak interconnect usage is 15%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "Read~1 " "Info: Following pins have the same output enable: Read~1" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[0\] LVTTL " "Info: Type bidirectional pin data\[0\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[0] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[1\] LVTTL " "Info: Type bidirectional pin data\[1\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[1] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[2\] LVTTL " "Info: Type bidirectional pin data\[2\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[2] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[3\] LVTTL " "Info: Type bidirectional pin data\[3\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[3] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[4\] LVTTL " "Info: Type bidirectional pin data\[4\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[4] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[5\] LVTTL " "Info: Type bidirectional pin data\[5\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[5] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[6\] LVTTL " "Info: Type bidirectional pin data\[6\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[6] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[7\] LVTTL " "Info: Type bidirectional pin data\[7\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[7] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[8\] LVTTL " "Info: Type bidirectional pin data\[8\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[8\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[8] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[9\] LVTTL " "Info: Type bidirectional pin data\[9\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[9\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[9] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[10\] LVTTL " "Info: Type bidirectional pin data\[10\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[10\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[10] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[11\] LVTTL " "Info: Type bidirectional pin data\[11\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[11\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[11] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[12\] LVTTL " "Info: Type bidirectional pin data\[12\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[12\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[12] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[13\] LVTTL " "Info: Type bidirectional pin data\[13\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[13\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[13] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[14\] LVTTL " "Info: Type bidirectional pin data\[14\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[14\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[14] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[15\] LVTTL " "Info: Type bidirectional pin data\[15\] uses the LVTTL I/O standard" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[15\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { data[15] } "NODE_NAME" } "" } } { "E:/dp_test/dp_test.fld" "" { Floorplan "E:/dp_test/dp_test.fld" "" "" { data[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 10 13:32:37 2008 " "Info: Processing ended: Wed Dec 10 13:32:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}