dp_test.map.qmsg

本程序是用VHDL语言编写的

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_servo_count dp_test.vhd(148) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(148): object \"A_servo_count\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 148 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "B_servo_count_clr dp_test.vhd(150) " "Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(150): object \"B_servo_count_clr\" assigned a value but never read" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 150 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_cp_clr dp_test.vhd(151) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(151): object \"B_servo_cp_clr\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 151 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpld_mcu_interupt dp_test.vhd(153) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(153): object \"cpld_mcu_interupt\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 153 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Servo_B_dir dp_test.vhd(31) " "Warning (10034): Output port \"Servo_B_dir\" at dp_test.vhd(31) has no driver" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 31 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Servo_B_cp dp_test.vhd(32) " "Warning (10034): Output port \"Servo_B_cp\" at dp_test.vhd(32) has no driver" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 32 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Servo_B_on dp_test.vhd(35) " "Warning (10034): Output port \"Servo_B_on\" at dp_test.vhd(35) has no driver" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 35 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Servo_B_clr dp_test.vhd(38) " "Warning (10034): Output port \"Servo_B_clr\" at dp_test.vhd(38) has no driver" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 38 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "A_sv_clr data_in GND " "Warning: Reduced register \"A_sv_clr\" with stuck data_in port to stuck value GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 273 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "A_frequecy\[0\] data_in GND " "Warning: Reduced register \"A_frequecy\[0\]\" with stuck data_in port to stuck value GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 360 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "A_servo_on High " "Info: Power-up level of register \"A_servo_on\" is not specified -- using power-up level of High to minimize register" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 273 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "A_servo_on data_in VCC " "Warning: Reduced register \"A_servo_on\" with stuck data_in port to stuck value VCC" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 273 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "A_phase_ctr data_in GND " "Warning: Reduced register \"A_phase_ctr\" with stuck data_in port to stuck value GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 88 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "A_servo_cp data_in GND " "Warning: Reduced register \"A_servo_cp\" with stuck data_in port to stuck value GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 386 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~28 Read~1 " "Info: Duplicate register \"Read~28\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~30 Read~1 " "Info: Duplicate register \"Read~30\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~26 Read~1 " "Info: Duplicate register \"Read~26\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~24 Read~1 " "Info: Duplicate register \"Read~24\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~22 Read~1 " "Info: Duplicate register \"Read~22\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~20 Read~1 " "Info: Duplicate register \"Read~20\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~18 Read~1 " "Info: Duplicate register \"Read~18\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~16 Read~1 " "Info: Duplicate register \"Read~16\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~14 Read~1 " "Info: Duplicate register \"Read~14\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~12 Read~1 " "Info: Duplicate register \"Read~12\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~10 Read~1 " "Info: Duplicate register \"Read~10\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~8 Read~1 " "Info: Duplicate register \"Read~8\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~6 Read~1 " "Info: Duplicate register \"Read~6\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~4 Read~1 " "Info: Duplicate register \"Read~4\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Read~2 Read~1 " "Info: Duplicate register \"Read~2\" merged to single register \"Read~1\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_A_cp GND " "Warning: Pin \"Servo_A_cp\" stuck at GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 29 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_B_dir GND " "Warning: Pin \"Servo_B_dir\" stuck at GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 31 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_B_cp GND " "Warning: Pin \"Servo_B_cp\" stuck at GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 32 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_A_on VCC " "Warning: Pin \"Servo_A_on\" stuck at VCC" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 34 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_B_on GND " "Warning: Pin \"Servo_B_on\" stuck at GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 35 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_A_clr GND " "Warning: Pin \"Servo_A_clr\" stuck at GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 37 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Servo_B_clr GND " "Warning: Pin \"Servo_B_clr\" stuck at GND" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 38 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Servo_A_Lock " "Warning: No output dependent on input pin \"Servo_A_Lock\"" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 40 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Servo_unable " "Warning: No output dependent on input pin \"Servo_unable\"" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 41 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "372 " "Info: Implemented 372 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "41 " "Info: Implemented 41 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "302 " "Info: Implemented 302 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 10 13:32:32 2008 " "Info: Processing ended: Wed Dec 10 13:32:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}