dp_test.map.qmsg

本程序是用VHDL语言编写的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 10 13:32:29 2008 " "Info: Processing started: Wed Dec 10 13:32:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dp_test -c dp_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dp_test -c dp_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dp_test.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dp_test.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dp_test-exam " "Info: Found design unit 1: dp_test-exam" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dp_test " "Info: Found entity 1: dp_test" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dp_test " "Info: Elaborating entity \"dp_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "A_sv_enable dp_test.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(73): object \"A_sv_enable\" assigned a value but never read" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 73 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "B_sv_enable dp_test.vhd(74) " "Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(74): object \"B_sv_enable\" assigned a value but never read" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 74 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_sv_clr dp_test.vhd(77) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(77): object \"B_sv_clr\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 77 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_on dp_test.vhd(80) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(80): object \"B_servo_on\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 80 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_dir dp_test.vhd(83) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(83): object \"B_servo_dir\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 83 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_cp dp_test.vhd(86) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(86): object \"B_servo_cp\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 86 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_phase_ctr dp_test.vhd(89) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(89): object \"B_phase_ctr\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 89 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_fre dp_test.vhd(92) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(92): object \"B_servo_fre\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 92 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_fre_buf dp_test.vhd(95) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(95): object \"B_fre_buf\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 95 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_stop dp_test.vhd(98) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(98): object \"B_servo_stop\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 98 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_run_state dp_test.vhd(101) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(101): object \"B_run_state\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 101 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_speed_ctr dp_test.vhd(104) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(104): object \"B_speed_ctr\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 104 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "B_servo_counter dp_test.vhd(107) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(107): object \"B_servo_counter\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 107 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "A_cw_test dp_test.vhd(135) " "Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(135): object \"A_cw_test\" assigned a value but never read" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 135 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "A_servo_pdir dp_test.vhd(139) " "Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(139): object \"A_servo_pdir\" assigned a value but never read" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 139 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_servo_cp_temp dp_test.vhd(145) " "Info (10035): Verilog HDL or VHDL information at dp_test.vhd(145): object \"A_servo_cp_temp\" declared but not used" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 145 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}