dp_test.tan.qmsg

本程序是用VHDL语言编写的

{ "Info" "ITDB_TH_RESULT" "data\[8\]~reg0 servo_poisition\[8\] clk 7.934 ns register " "Info: th for register \"data\[8\]~reg0\" (data pin = \"servo_poisition\[8\]\", clock pin = \"clk\") is 7.934 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.722 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_144 33 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { clk } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(1.294 ns) 8.819 ns clk_in 2 REG LC_X11_Y5_N2 84 " "Info: 2: + IC(6.393 ns) + CELL(1.294 ns) = 8.819 ns; Loc. = LC_X11_Y5_N2; Fanout = 84; REG Node = 'clk_in'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.687 ns" { clk clk_in } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.985 ns) + CELL(0.918 ns) 13.722 ns data\[8\]~reg0 3 REG LC_X11_Y6_N4 1 " "Info: 3: + IC(3.985 ns) + CELL(0.918 ns) = 13.722 ns; Loc. = LC_X11_Y6_N4; Fanout = 1; REG Node = 'data\[8\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.903 ns" { clk_in data[8]~reg0 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 24.37 % ) " "Info: Total cell delay = 3.344 ns ( 24.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.378 ns ( 75.63 % ) " "Info: Total interconnect delay = 10.378 ns ( 75.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in data[8]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in data[8]~reg0 } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.009 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns servo_poisition\[8\] 1 PIN PIN_98 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_98; Fanout = 1; PIN Node = 'servo_poisition\[8\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { servo_poisition[8] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.591 ns) 6.009 ns data\[8\]~reg0 2 REG LC_X11_Y6_N4 1 " "Info: 2: + IC(4.286 ns) + CELL(0.591 ns) = 6.009 ns; Loc. = LC_X11_Y6_N4; Fanout = 1; REG Node = 'data\[8\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.877 ns" { servo_poisition[8] data[8]~reg0 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 178 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 28.67 % ) " "Info: Total cell delay = 1.723 ns ( 28.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.286 ns ( 71.33 % ) " "Info: Total interconnect delay = 4.286 ns ( 71.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.009 ns" { servo_poisition[8] data[8]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.009 ns" { servo_poisition[8] servo_poisition[8]~combout data[8]~reg0 } { 0.000ns 0.000ns 4.286ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in data[8]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in data[8]~reg0 } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.009 ns" { servo_poisition[8] data[8]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.009 ns" { servo_poisition[8] servo_poisition[8]~combout data[8]~reg0 } { 0.000ns 0.000ns 4.286ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 10 13:32:42 2008 " "Info: Processing ended: Wed Dec 10 13:32:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}