📄 dp_test.tan.qmsg

📁 本程序是用VHDL语言编写的
💻 QMSG
📖 第 1 页 / 共 4 页
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Servo_Phase_A register A_servo_cp_ccw\[3\] register A_servo_cp_ccw\[12\] 201.09 MHz 4.973 ns Internal " "Info: Clock \"Servo_Phase_A\" has Internal fmax of 201.09 MHz between source register \"A_servo_cp_ccw\[3\]\" and destination register \"A_servo_cp_ccw\[12\]\" (period= 4.973 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.264 ns + Longest register register " "Info: + Longest register to register delay is 4.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns A_servo_cp_ccw\[3\] 1 REG LC_X14_Y4_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y4_N5; Fanout = 6; REG Node = 'A_servo_cp_ccw\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { A_servo_cp_ccw[3] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.978 ns) 1.870 ns A_servo_cp_ccw\[3\]~141 2 COMB LC_X14_Y4_N5 2 " "Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X14_Y4_N5; Fanout = 2; COMB Node = 'A_servo_cp_ccw\[3\]~141'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "1.870 ns" { A_servo_cp_ccw[3] A_servo_cp_ccw[3]~141 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.993 ns A_servo_cp_ccw\[4\]~145 3 COMB LC_X14_Y4_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X14_Y4_N6; Fanout = 2; COMB Node = 'A_servo_cp_ccw\[4\]~145'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.123 ns" { A_servo_cp_ccw[3]~141 A_servo_cp_ccw[4]~145 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.116 ns A_servo_cp_ccw\[5\]~149 4 COMB LC_X14_Y4_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X14_Y4_N7; Fanout = 2; COMB Node = 'A_servo_cp_ccw\[5\]~149'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.123 ns" { A_servo_cp_ccw[4]~145 A_servo_cp_ccw[5]~149 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.239 ns A_servo_cp_ccw\[6\]~153 5 COMB LC_X14_Y4_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X14_Y4_N8; Fanout = 2; COMB Node = 'A_servo_cp_ccw\[6\]~153'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.123 ns" { A_servo_cp_ccw[5]~149 A_servo_cp_ccw[6]~153 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 2.638 ns A_servo_cp_ccw\[7\]~157 6 COMB LC_X14_Y4_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X14_Y4_N9; Fanout = 6; COMB Node = 'A_servo_cp_ccw\[7\]~157'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.399 ns" { A_servo_cp_ccw[6]~153 A_servo_cp_ccw[7]~157 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.264 ns A_servo_cp_ccw\[12\] 7 REG LC_X15_Y4_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X15_Y4_N4; Fanout = 4; REG Node = 'A_servo_cp_ccw\[12\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "1.626 ns" { A_servo_cp_ccw[7]~157 A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.372 ns ( 79.08 % ) " "Info: Total cell delay = 3.372 ns ( 79.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.892 ns ( 20.92 % ) " "Info: Total interconnect delay = 0.892 ns ( 20.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.264 ns" { A_servo_cp_ccw[3] A_servo_cp_ccw[3]~141 A_servo_cp_ccw[4]~145 A_servo_cp_ccw[5]~149 A_servo_cp_ccw[6]~153 A_servo_cp_ccw[7]~157 A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.264 ns" { A_servo_cp_ccw[3] A_servo_cp_ccw[3]~141 A_servo_cp_ccw[4]~145 A_servo_cp_ccw[5]~149 A_servo_cp_ccw[6]~153 A_servo_cp_ccw[7]~157 A_servo_cp_ccw[12] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Servo_Phase_A destination 7.564 ns + Shortest register " "Info: + Shortest clock path from clock \"Servo_Phase_A\" to destination register is 7.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Servo_Phase_A 1 CLK PIN_30 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_30; Fanout = 34; CLK Node = 'Servo_Phase_A'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { Servo_Phase_A } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.514 ns) + CELL(0.918 ns) 7.564 ns A_servo_cp_ccw\[12\] 2 REG LC_X15_Y4_N4 4 " "Info: 2: + IC(5.514 ns) + CELL(0.918 ns) = 7.564 ns; Loc. = LC_X15_Y4_N4; Fanout = 4; REG Node = 'A_servo_cp_ccw\[12\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.432 ns" { Servo_Phase_A A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.10 % ) " "Info: Total cell delay = 2.050 ns ( 27.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.514 ns ( 72.90 % ) " "Info: Total interconnect delay = 5.514 ns ( 72.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.564 ns" { Servo_Phase_A A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.564 ns" { Servo_Phase_A Servo_Phase_A~combout A_servo_cp_ccw[12] } { 0.000ns 0.000ns 5.514ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Servo_Phase_A source 7.564 ns - Longest register " "Info: - Longest clock path from clock \"Servo_Phase_A\" to source register is 7.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Servo_Phase_A 1 CLK PIN_30 34 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_30; Fanout = 34; CLK Node = 'Servo_Phase_A'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { Servo_Phase_A } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.514 ns) + CELL(0.918 ns) 7.564 ns A_servo_cp_ccw\[3\] 2 REG LC_X14_Y4_N5 6 " "Info: 2: + IC(5.514 ns) + CELL(0.918 ns) = 7.564 ns; Loc. = LC_X14_Y4_N5; Fanout = 6; REG Node = 'A_servo_cp_ccw\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.432 ns" { Servo_Phase_A A_servo_cp_ccw[3] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.10 % ) " "Info: Total cell delay = 2.050 ns ( 27.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.514 ns ( 72.90 % ) " "Info: Total interconnect delay = 5.514 ns ( 72.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.564 ns" { Servo_Phase_A A_servo_cp_ccw[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.564 ns" { Servo_Phase_A Servo_Phase_A~combout A_servo_cp_ccw[3] } { 0.000ns 0.000ns 5.514ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.564 ns" { Servo_Phase_A A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.564 ns" { Servo_Phase_A Servo_Phase_A~combout A_servo_cp_ccw[12] } { 0.000ns 0.000ns 5.514ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.564 ns" { Servo_Phase_A A_servo_cp_ccw[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.564 ns" { Servo_Phase_A Servo_Phase_A~combout A_servo_cp_ccw[3] } { 0.000ns 0.000ns 5.514ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 451 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.264 ns" { A_servo_cp_ccw[3] A_servo_cp_ccw[3]~141 A_servo_cp_ccw[4]~145 A_servo_cp_ccw[5]~149 A_servo_cp_ccw[6]~153 A_servo_cp_ccw[7]~157 A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.264 ns" { A_servo_cp_ccw[3] A_servo_cp_ccw[3]~141 A_servo_cp_ccw[4]~145 A_servo_cp_ccw[5]~149 A_servo_cp_ccw[6]~153 A_servo_cp_ccw[7]~157 A_servo_cp_ccw[12] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.564 ns" { Servo_Phase_A A_servo_cp_ccw[12] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.564 ns" { Servo_Phase_A Servo_Phase_A~combout A_servo_cp_ccw[12] } { 0.000ns 0.000ns 5.514ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.564 ns" { Servo_Phase_A A_servo_cp_ccw[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.564 ns" { Servo_Phase_A Servo_Phase_A~combout A_servo_cp_ccw[3] } { 0.000ns 0.000ns 5.514ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "A_servo\[1\] mcu_nwr clk -0.813 ns register " "Info: tsu for register \"A_servo\[1\]\" (data pin = \"mcu_nwr\", clock pin = \"clk\") is -0.813 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.576 ns + Longest pin register " "Info: + Longest pin to register delay is 12.576 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mcu_nwr 1 PIN PIN_71 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'mcu_nwr'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { mcu_nwr } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.593 ns) + CELL(0.914 ns) 6.639 ns A_servo_count_clr\[1\]~56 2 COMB LC_X12_Y4_N4 2 " "Info: 2: + IC(4.593 ns) + CELL(0.914 ns) = 6.639 ns; Loc. = LC_X12_Y4_N4; Fanout = 2; COMB Node = 'A_servo_count_clr\[1\]~56'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "5.507 ns" { mcu_nwr A_servo_count_clr[1]~56 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 7.373 ns A_moto\[0\]~108 3 COMB LC_X12_Y4_N5 2 " "Info: 3: + IC(0.534 ns) + CELL(0.200 ns) = 7.373 ns; Loc. = LC_X12_Y4_N5; Fanout = 2; COMB Node = 'A_moto\[0\]~108'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.734 ns" { A_servo_count_clr[1]~56 A_moto[0]~108 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.661 ns) + CELL(0.200 ns) 10.234 ns A_servo\[7\]~118 4 COMB LC_X16_Y7_N0 8 " "Info: 4: + IC(2.661 ns) + CELL(0.200 ns) = 10.234 ns; Loc. = LC_X16_Y7_N0; Fanout = 8; COMB Node = 'A_servo\[7\]~118'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "2.861 ns" { A_moto[0]~108 A_servo[7]~118 } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(1.243 ns) 12.576 ns A_servo\[1\] 5 REG LC_X15_Y7_N4 3 " "Info: 5: + IC(1.099 ns) + CELL(1.243 ns) = 12.576 ns; Loc. = LC_X15_Y7_N4; Fanout = 3; REG Node = 'A_servo\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "2.342 ns" { A_servo[7]~118 A_servo[1] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.689 ns ( 29.33 % ) " "Info: Total cell delay = 3.689 ns ( 29.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.887 ns ( 70.67 % ) " "Info: Total interconnect delay = 8.887 ns ( 70.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "12.576 ns" { mcu_nwr A_servo_count_clr[1]~56 A_moto[0]~108 A_servo[7]~118 A_servo[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.576 ns" { mcu_nwr mcu_nwr~combout A_servo_count_clr[1]~56 A_moto[0]~108 A_servo[7]~118 A_servo[1] } { 0.000ns 0.000ns 4.593ns 0.534ns 2.661ns 1.099ns } { 0.000ns 1.132ns 0.914ns 0.200ns 0.200ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.722 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 13.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_144 33 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { clk } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(1.294 ns) 8.819 ns clk_in 2 REG LC_X11_Y5_N2 84 " "Info: 2: + IC(6.393 ns) + CELL(1.294 ns) = 8.819 ns; Loc. = LC_X11_Y5_N2; Fanout = 84; REG Node = 'clk_in'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.687 ns" { clk clk_in } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.985 ns) + CELL(0.918 ns) 13.722 ns A_servo\[1\] 3 REG LC_X15_Y7_N4 3 " "Info: 3: + IC(3.985 ns) + CELL(0.918 ns) = 13.722 ns; Loc. = LC_X15_Y7_N4; Fanout = 3; REG Node = 'A_servo\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.903 ns" { clk_in A_servo[1] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 24.37 % ) " "Info: Total cell delay = 3.344 ns ( 24.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.378 ns ( 75.63 % ) " "Info: Total interconnect delay = 10.378 ns ( 75.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_servo[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_servo[1] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "12.576 ns" { mcu_nwr A_servo_count_clr[1]~56 A_moto[0]~108 A_servo[7]~118 A_servo[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.576 ns" { mcu_nwr mcu_nwr~combout A_servo_count_clr[1]~56 A_moto[0]~108 A_servo[7]~118 A_servo[1] } { 0.000ns 0.000ns 4.593ns 0.534ns 2.661ns 1.099ns } { 0.000ns 1.132ns 0.914ns 0.200ns 0.200ns 1.243ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_servo[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_servo[1] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Moto_A_dir A_moto\[2\] 20.837 ns register " "Info: tco from clock \"clk\" to destination pin \"Moto_A_dir\" through register \"A_moto\[2\]\" is 20.837 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.722 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 13.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_144 33 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { clk } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(1.294 ns) 8.819 ns clk_in 2 REG LC_X11_Y5_N2 84 " "Info: 2: + IC(6.393 ns) + CELL(1.294 ns) = 8.819 ns; Loc. = LC_X11_Y5_N2; Fanout = 84; REG Node = 'clk_in'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.687 ns" { clk clk_in } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.985 ns) + CELL(0.918 ns) 13.722 ns A_moto\[2\] 3 REG LC_X16_Y7_N8 1 " "Info: 3: + IC(3.985 ns) + CELL(0.918 ns) = 13.722 ns; Loc. = LC_X16_Y7_N8; Fanout = 1; REG Node = 'A_moto\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.903 ns" { clk_in A_moto[2] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 24.37 % ) " "Info: Total cell delay = 3.344 ns ( 24.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.378 ns ( 75.63 % ) " "Info: Total interconnect delay = 10.378 ns ( 75.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto[2] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.739 ns + Longest register pin " "Info: + Longest register to pin delay is 6.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns A_moto\[2\] 1 REG LC_X16_Y7_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y7_N8; Fanout = 1; REG Node = 'A_moto\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { A_moto[2] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 195 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.877 ns) + CELL(0.914 ns) 1.791 ns A_moto_dir~29 2 COMB LC_X16_Y7_N3 34 " "Info: 2: + IC(0.877 ns) + CELL(0.914 ns) = 1.791 ns; Loc. = LC_X16_Y7_N3; Fanout = 34; COMB Node = 'A_moto_dir~29'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "1.791 ns" { A_moto[2] A_moto_dir~29 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 2.296 ns A_moto_dir~30 3 COMB LC_X16_Y7_N4 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 2.296 ns; Loc. = LC_X16_Y7_N4; Fanout = 1; COMB Node = 'A_moto_dir~30'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.505 ns" { A_moto_dir~29 A_moto_dir~30 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.121 ns) + CELL(2.322 ns) 6.739 ns Moto_A_dir 4 PIN PIN_108 0 " "Info: 4: + IC(2.121 ns) + CELL(2.322 ns) = 6.739 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'Moto_A_dir'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.443 ns" { A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.436 ns ( 50.99 % ) " "Info: Total cell delay = 3.436 ns ( 50.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.303 ns ( 49.01 % ) " "Info: Total interconnect delay = 3.303 ns ( 49.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.739 ns" { A_moto[2] A_moto_dir~29 A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.739 ns" { A_moto[2] A_moto_dir~29 A_moto_dir~30 Moto_A_dir } { 0.000ns 0.877ns 0.305ns 2.121ns } { 0.000ns 0.914ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto[2] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "6.739 ns" { A_moto[2] A_moto_dir~29 A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.739 ns" { A_moto[2] A_moto_dir~29 A_moto_dir~30 Moto_A_dir } { 0.000ns 0.877ns 0.305ns 2.121ns } { 0.000ns 0.914ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rst Moto_A_dir 10.964 ns Longest " "Info: Longest tpd from source pin \"rst\" to destination pin \"Moto_A_dir\" is 10.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_32 17 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_32; Fanout = 17; PIN Node = 'rst'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { rst } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.684 ns) + CELL(0.200 ns) 6.016 ns A_moto_dir~29 2 COMB LC_X16_Y7_N3 34 " "Info: 2: + IC(4.684 ns) + CELL(0.200 ns) = 6.016 ns; Loc. = LC_X16_Y7_N3; Fanout = 34; COMB Node = 'A_moto_dir~29'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.884 ns" { rst A_moto_dir~29 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.521 ns A_moto_dir~30 3 COMB LC_X16_Y7_N4 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 6.521 ns; Loc. = LC_X16_Y7_N4; Fanout = 1; COMB Node = 'A_moto_dir~30'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "0.505 ns" { A_moto_dir~29 A_moto_dir~30 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.121 ns) + CELL(2.322 ns) 10.964 ns Moto_A_dir 4 PIN PIN_108 0 " "Info: 4: + IC(2.121 ns) + CELL(2.322 ns) = 10.964 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'Moto_A_dir'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.443 ns" { A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.854 ns ( 35.15 % ) " "Info: Total cell delay = 3.854 ns ( 35.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.110 ns ( 64.85 % ) " "Info: Total interconnect delay = 7.110 ns ( 64.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "10.964 ns" { rst A_moto_dir~29 A_moto_dir~30 Moto_A_dir } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.964 ns" { rst rst~combout A_moto_dir~29 A_moto_dir~30 Moto_A_dir } { 0.000ns 0.000ns 4.684ns 0.305ns 2.121ns } { 0.000ns 1.132ns 0.200ns 0.200ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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