dp_test.tan.qmsg

本程序是用VHDL语言编写的

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 10 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Servo_Phase_A " "Info: Assuming node \"Servo_Phase_A\" is an undefined clock" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 43 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Servo_Phase_A" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_in " "Info: Detected ripple clock \"clk_in\" as buffer" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 159 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk_in" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register A_moto_count\[7\] register A_moto_cp 101.47 MHz 9.855 ns Internal " "Info: Clock \"clk\" has Internal fmax of 101.47 MHz between source register \"A_moto_count\[7\]\" and destination register \"A_moto_cp\" (period= 9.855 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.146 ns + Longest register register " "Info: + Longest register to register delay is 9.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns A_moto_count\[7\] 1 REG LC_X12_Y6_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y6_N5; Fanout = 4; REG Node = 'A_moto_count\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { A_moto_count[7] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 239 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.265 ns) + CELL(0.200 ns) 2.465 ns rtl~543 2 COMB LC_X12_Y6_N9 1 " "Info: 2: + IC(2.265 ns) + CELL(0.200 ns) = 2.465 ns; Loc. = LC_X12_Y6_N9; Fanout = 1; COMB Node = 'rtl~543'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "2.465 ns" { A_moto_count[7] rtl~543 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.875 ns) + CELL(0.740 ns) 5.080 ns rtl~545 3 COMB LC_X13_Y6_N9 4 " "Info: 3: + IC(1.875 ns) + CELL(0.740 ns) = 5.080 ns; Loc. = LC_X13_Y6_N9; Fanout = 4; COMB Node = 'rtl~545'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "2.615 ns" { rtl~543 rtl~545 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.552 ns) + CELL(0.200 ns) 7.832 ns rtl~1 4 COMB LC_X15_Y7_N9 1 " "Info: 4: + IC(2.552 ns) + CELL(0.200 ns) = 7.832 ns; Loc. = LC_X15_Y7_N9; Fanout = 1; COMB Node = 'rtl~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "2.752 ns" { rtl~545 rtl~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.591 ns) 9.146 ns A_moto_cp 5 REG LC_X15_Y7_N0 2 " "Info: 5: + IC(0.723 ns) + CELL(0.591 ns) = 9.146 ns; Loc. = LC_X15_Y7_N0; Fanout = 2; REG Node = 'A_moto_cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "1.314 ns" { rtl~1 A_moto_cp } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 239 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.731 ns ( 18.93 % ) " "Info: Total cell delay = 1.731 ns ( 18.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.415 ns ( 81.07 % ) " "Info: Total interconnect delay = 7.415 ns ( 81.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "9.146 ns" { A_moto_count[7] rtl~543 rtl~545 rtl~1 A_moto_cp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.146 ns" { A_moto_count[7] rtl~543 rtl~545 rtl~1 A_moto_cp } { 0.000ns 2.265ns 1.875ns 2.552ns 0.723ns } { 0.000ns 0.200ns 0.740ns 0.200ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.722 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 13.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_144 33 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { clk } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(1.294 ns) 8.819 ns clk_in 2 REG LC_X11_Y5_N2 84 " "Info: 2: + IC(6.393 ns) + CELL(1.294 ns) = 8.819 ns; Loc. = LC_X11_Y5_N2; Fanout = 84; REG Node = 'clk_in'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.687 ns" { clk clk_in } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.985 ns) + CELL(0.918 ns) 13.722 ns A_moto_cp 3 REG LC_X15_Y7_N0 2 " "Info: 3: + IC(3.985 ns) + CELL(0.918 ns) = 13.722 ns; Loc. = LC_X15_Y7_N0; Fanout = 2; REG Node = 'A_moto_cp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.903 ns" { clk_in A_moto_cp } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 239 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 24.37 % ) " "Info: Total cell delay = 3.344 ns ( 24.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.378 ns ( 75.63 % ) " "Info: Total interconnect delay = 10.378 ns ( 75.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto_cp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto_cp } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.722 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_144 33 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 33; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "" { clk } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(1.294 ns) 8.819 ns clk_in 2 REG LC_X11_Y5_N2 84 " "Info: 2: + IC(6.393 ns) + CELL(1.294 ns) = 8.819 ns; Loc. = LC_X11_Y5_N2; Fanout = 84; REG Node = 'clk_in'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "7.687 ns" { clk clk_in } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.985 ns) + CELL(0.918 ns) 13.722 ns A_moto_count\[7\] 3 REG LC_X12_Y6_N5 4 " "Info: 3: + IC(3.985 ns) + CELL(0.918 ns) = 13.722 ns; Loc. = LC_X12_Y6_N5; Fanout = 4; REG Node = 'A_moto_count\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "4.903 ns" { clk_in A_moto_count[7] } "NODE_NAME" } "" } } { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 239 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 24.37 % ) " "Info: Total cell delay = 3.344 ns ( 24.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.378 ns ( 75.63 % ) " "Info: Total interconnect delay = 10.378 ns ( 75.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto_count[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto_count[7] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto_cp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto_cp } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto_count[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto_count[7] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 239 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "dp_test.vhd" "" { Text "E:/dp_test/dp_test.vhd" 239 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "9.146 ns" { A_moto_count[7] rtl~543 rtl~545 rtl~1 A_moto_cp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.146 ns" { A_moto_count[7] rtl~543 rtl~545 rtl~1 A_moto_cp } { 0.000ns 2.265ns 1.875ns 2.552ns 0.723ns } { 0.000ns 0.200ns 0.740ns 0.200ns 0.591ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto_cp } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto_cp } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dp_test" "UNKNOWN" "V1" "E:/dp_test/db/dp_test.quartus_db" { Floorplan "E:/dp_test/" "" "13.722 ns" { clk clk_in A_moto_count[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.722 ns" { clk clk~combout clk_in A_moto_count[7] } { 0.000ns 0.000ns 6.393ns 3.985ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}