dp_test.fit.summary

本程序是用VHDL语言编写的

Fitter Status : Successful - Wed Dec 10 13:32:37 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : dp_test
Top-level Entity Name : dp_test
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 275 / 1,270 ( 22 % )
Total pins : 70 / 116 ( 60 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )