dp_test.map.rpt

本程序是用VHDL语言编写的

;     -- asynchronous clear/load mode         ; 33     ;
;                                             ;        ;
; Total registers                             ; 148    ;
; Total logic cells in carry chains           ; 128    ;
; I/O pins                                    ; 70     ;
; Maximum fan-out node                        ; clk_in ;
; Maximum fan-out                             ; 84     ;
; Total fan-out                               ; 995    ;
; Average fan-out                             ; 2.67   ;
+---------------------------------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |dp_test                   ; 302 (302)   ; 148          ; 0          ; 70   ; 0            ; 154 (154)    ; 73 (73)           ; 75 (75)          ; 128 (128)       ; 0 (0)      ; |dp_test            ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 148   ;
; Number of registers using Synchronous Clear  ; 27    ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 33    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 79    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |dp_test|A_moto[0]         ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |dp_test|A_servo[7]        ;
; 64:1               ; 6 bits    ; 252 LEs       ; 12 LEs               ; 240 LEs                ; Yes        ; |dp_test|data[10]~reg0     ;
; 64:1               ; 10 bits   ; 420 LEs       ; 20 LEs               ; 400 LEs                ; Yes        ; |dp_test|data[3]~reg0      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |dp_test ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; n              ; 4     ; Integer                                        ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/dp_test/dp_test.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 10 13:32:29 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dp_test -c dp_test
Info: Found 2 design units, including 1 entities, in source file dp_test.vhd
    Info: Found design unit 1: dp_test-exam
    Info: Found entity 1: dp_test
Info: Elaborating entity "dp_test" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(73): object "A_sv_enable" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(74): object "B_sv_enable" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(77): object "B_sv_clr" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(80): object "B_servo_on" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(83): object "B_servo_dir" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(86): object "B_servo_cp" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(89): object "B_phase_ctr" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(92): object "B_servo_fre" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(95): object "B_fre_buf" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(98): object "B_servo_stop" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(101): object "B_run_state" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(104): object "B_speed_ctr" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(107): object "B_servo_counter" declared but not used
Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(135): object "A_cw_test" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(139): object "A_servo_pdir" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(145): object "A_servo_cp_temp" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(148): object "A_servo_count" declared but not used
Warning (10036): Verilog HDL or VHDL warning at dp_test.vhd(150): object "B_servo_count_clr" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(151): object "B_servo_cp_clr" declared but not used
Info (10035): Verilog HDL or VHDL information at dp_test.vhd(153): object "cpld_mcu_interupt" declared but not used
Warning (10034): Output port "Servo_B_dir" at dp_test.vhd(31) has no driver
Warning (10034): Output port "Servo_B_cp" at dp_test.vhd(32) has no driver
Warning (10034): Output port "Servo_B_on" at dp_test.vhd(35) has no driver
Warning (10034): Output port "Servo_B_clr" at dp_test.vhd(38) has no driver
Warning: Reduced register "A_sv_clr" with stuck data_in port to stuck value GND
Warning: Reduced register "A_frequecy[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "A_servo_on" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "A_servo_on" with stuck data_in port to stuck value VCC
Warning: Reduced register "A_phase_ctr" with stuck data_in port to stuck value GND
Warning: Reduced register "A_servo_cp" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "Read~28" merged to single register "Read~1"
    Info: Duplicate register "Read~30" merged to single register "Read~1"
    Info: Duplicate register "Read~26" merged to single register "Read~1"
    Info: Duplicate register "Read~24" merged to single register "Read~1"
    Info: Duplicate register "Read~22" merged to single register "Read~1"
    Info: Duplicate register "Read~20" merged to single register "Read~1"
    Info: Duplicate register "Read~18" merged to single register "Read~1"
    Info: Duplicate register "Read~16" merged to single register "Read~1"
    Info: Duplicate register "Read~14" merged to single register "Read~1"
    Info: Duplicate register "Read~12" merged to single register "Read~1"
    Info: Duplicate register "Read~10" merged to single register "Read~1"
    Info: Duplicate register "Read~8" merged to single register "Read~1"
    Info: Duplicate register "Read~6" merged to single register "Read~1"
    Info: Duplicate register "Read~4" merged to single register "Read~1"
    Info: Duplicate register "Read~2" merged to single register "Read~1"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "Servo_A_cp" stuck at GND
    Warning: Pin "Servo_B_dir" stuck at GND
    Warning: Pin "Servo_B_cp" stuck at GND
    Warning: Pin "Servo_A_on" stuck at VCC
    Warning: Pin "Servo_B_on" stuck at GND
    Warning: Pin "Servo_A_clr" stuck at GND
    Warning: Pin "Servo_B_clr" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "Servo_A_Lock"
    Warning: No output dependent on input pin "Servo_unable"
Info: Implemented 372 device resources after synthesis - the final resource count might be different
    Info: Implemented 41 input pins
    Info: Implemented 13 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 302 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Processing ended: Wed Dec 10 13:32:32 2008
    Info: Elapsed time: 00:00:03