code.v

Verilog的LED控制器源程序

module sensor(RESET,SX,SY,SZ,RECEIVE,STATUS,DATA);

input RESET; // power on reset
input [11:0]SX;//sensor x axis ;12bit
input [11:0]SY;//sensor y axis ;12bit
input [5:0]SZ;//sensor Z axis  ;6bit

input RECEIVE;
output STATUS;
output [9:0]DATA;
reg [9:0]ADD;
reg STATUS;
reg [9:0]DATA;
reg [4:0]cnt;
reg [1:0]m;

always @ (posedge RECEIVE or negedge RESET)
begin
	if (!RESET)
	 begin
		STATUS=1'b0; DATA=10'b1111111111; cnt=5'b00000; 
		ADD=0;m=0;
	 end
	else
	 begin
      case (m)
			0: begin m=1; end
			1: begin
			    cnt=cnt+1; STATUS=1'b1;
				case(cnt)
				   1:begin ADD[0] = SX[0] & SY[0]; ADD[1] = SX[1] & SY[0]; 
				           ADD[2] = SX[2] & SY[0]; ADD[3] = SX[3] & SY[0];
				           ADD[4] = SX[4] & SY[0]; ADD[5] = SX[5] & SY[0]; 
				           ADD[6] = SX[6] & SY[0]; ADD[7] = SX[7] & SY[0];
				           ADD[8] = SX[8] & SY[0]; ADD[9] = SX[9] & SY[0]; 
				           DATA[9:0]=ADD[9:0]; m=1;
				     end		
				   2:begin ADD[0] = SX[10] & SY[0]; ADD[1] = SX[11] & SY[0];
                           ADD[2] = SX[0] & SY[1]; ADD[3] = SX[1] & SY[1]; 
                           ADD[4] = SX[2] & SY[1]; ADD[5] = SX[3] & SY[1];
                           ADD[6] = SX[4] & SY[1]; ADD[7] = SX[5] & SY[1]; 
                           ADD[8] = SX[6] & SY[1]; ADD[9] = SX[7] & SY[1];
				           DATA=ADD[9:0]; m=1;
				     end
				   3:begin ADD[0] = SX[8] & SY[1]; ADD[1] = SX[9] & SY[1]; 
                           ADD[2] = SX[10] & SY[1];ADD[3] = SX[11] & SY[1];
                           ADD[4] = SX[0] & SY[2]; ADD[5] = SX[1] & SY[2]; 
                           ADD[6] = SX[2] & SY[2]; ADD[7] = SX[3] & SY[2];
                           ADD[8] = SX[4] & SY[2]; ADD[9] = SX[5] & SY[2]; 				
				           DATA=ADD[9:0];m=1;
				     end
				   4:begin ADD[0] = SX[6] & SY[2]; ADD[1] = SX[7] & SY[2];
                           ADD[2] = SX[8] & SY[2]; ADD[3] = SX[9] & SY[2]; 
                           ADD[4] = SX[10] & SY[2];ADD[5] = SX[11] & SY[2];
                           ADD[6] = SX[0] & SY[3]; ADD[7] = SX[1] & SY[3]; 
                           ADD[8] = SX[2] & SY[3]; ADD[9] = SX[3] & SY[3];
				           DATA=ADD[9:0];m=1;
				     end
				   5:begin ADD[0] = SX[4] & SY[3]; ADD[1] = SX[5] & SY[3]; 
				           ADD[2] = SX[6] & SY[3]; ADD[3] = SX[7] & SY[3];
				           ADD[4] = SX[8] & SY[3]; ADD[5] = SX[9] & SY[3]; 
				           ADD[6] = SX[10] & SY[3];ADD[7] = SX[11] & SY[3];
				           ADD[8] = SX[0] & SY[4]; ADD[9] = SX[1] & SY[4];
				           DATA=ADD[9:0];m=1;
				     end
				   6:begin ADD[0] = SX[2] & SY[4]; ADD[1] = SX[3] & SY[4];
				           ADD[2] = SX[4] & SY[4]; ADD[3] = SX[5] & SY[4]; 
				           ADD[4] = SX[6] & SY[4]; ADD[5] = SX[7] & SY[4];
				           ADD[6] = SX[8] & SY[4]; ADD[7] = SX[9] & SY[4]; 
				           ADD[8] = SX[10] & SY[4];ADD[9] = SX[11] & SY[4];
				           DATA=ADD[9:0];m=1;
				     end
				   7:begin ADD[0] = SX[0] & SY[5]; ADD[1] = SX[1] & SY[5]; 
				           ADD[2] = SX[2] & SY[5]; ADD[3] = SX[3] & SY[5];
				           ADD[4] = SX[4] & SY[5]; ADD[5] = SX[5] & SY[5]; 
				           ADD[6] = SX[6] & SY[5]; ADD[7] = SX[7] & SY[5];
				           ADD[8] = SX[8] & SY[5]; ADD[9] = SX[9] & SY[5]; 
				           DATA=ADD[9:0];m=1;
				     end
				   8:begin ADD[0] = SX[10] & SY[5];ADD[1] = SX[11] & SY[5];
				           ADD[2] = SX[0] & SY[6]; ADD[3] = SX[1] & SY[6]; 
				           ADD[4] = SX[2] & SY[6]; ADD[5] = SX[3] & SY[6];
				           ADD[6] = SX[4] & SY[6]; ADD[7] = SX[5] & SY[6]; 
				           ADD[8] = SX[6] & SY[6]; ADD[9] = SX[7] & SY[6];
				           DATA=ADD[9:0];m=1;
				     end
				   9:begin ADD[0] = SX[8] & SY[6]; ADD[1] = SX[9] & SY[6]; 
				           ADD[2] = SX[10] & SY[6];ADD[3] = SX[11] & SY[6];
				           ADD[4] = SX[0] & SY[7]; ADD[5] = SX[1] & SY[7]; 
				           ADD[6] = SX[2] & SY[7]; ADD[7] = SX[3] & SY[7];
				           ADD[8] = SX[4] & SY[7]; ADD[9] = SX[5] & SY[7]; 
				           DATA=ADD[9:0];m=1;
				     end
				  10:begin ADD[0] = SX[6] & SY[7]; ADD[1] = SX[7] & SY[7];
				           ADD[2] = SX[8] & SY[7]; ADD[3] = SX[9] & SY[7]; 
				           ADD[4] = SX[10] & SY[7];ADD[5] = SX[11] & SY[7];
				           ADD[6] = SX[0] & SY[8]; ADD[7] = SX[1] & SY[8]; 
				           ADD[8] = SX[2] & SY[8]; ADD[9] = SX[3] & SY[8];
				           DATA=ADD[9:0];m=1;
				     end
				  11:begin ADD[0] = SX[4] & SY[8]; ADD[1] = SX[5] & SY[8]; 
				           ADD[2] = SX[6] & SY[8]; ADD[3] = SX[7] & SY[8];
				           ADD[4] = SX[8] & SY[8]; ADD[5] = SX[9] & SY[8]; 
				           ADD[6] = SX[10] & SY[8];ADD[7] = SX[11] & SY[8];
				           ADD[8] = SX[0] & SY[9]; ADD[9] = SX[1] & SY[9]; 	
				           DATA=ADD[9:0];m=1;
				     end				
				  12:begin ADD[0] = SX[2] & SY[9]; ADD[1] = SX[3] & SY[9];
				           ADD[2] = SX[4] & SY[9]; ADD[3] = SX[5] & SY[9]; 
				           ADD[4] = SX[6] & SY[9]; ADD[5] = SX[7] & SY[9];
				           ADD[6] = SX[8] & SY[9]; ADD[7] = SX[9] & SY[9]; 
				           ADD[8] = SX[10] & SY[9];ADD[9] = SX[11] & SY[9];
				           DATA=ADD[9:0];m=1;
				     end																
				  13:begin ADD[0] = SX[0] & SY[10]; ADD[1] = SX[1] & SY[10]; 
				           ADD[2] = SX[2] & SY[10]; ADD[3] = SX[3] & SY[10];
				           ADD[4] = SX[4] & SY[10]; ADD[5] = SX[5] & SY[10]; 
				           ADD[6] = SX[6] & SY[10]; ADD[7] = SX[7] & SY[10];
				           ADD[8] = SX[8] & SY[10]; ADD[9] = SX[9] & SY[10];  
				           DATA=ADD[9:0];m=1;
				     end
				  14:begin ADD[0] = SX[10] & SY[10];ADD[1] = SX[11] & SY[10];
				           ADD[2] = SX[0] & SY[11]; ADD[3] = SX[1] & SY[11]; 
				           ADD[4] = SX[2] & SY[11]; ADD[5] = SX[3] & SY[11];
				           ADD[6] = SX[4] & SY[11]; ADD[7] = SX[5] & SY[11]; 
				           ADD[8] = SX[6] & SY[11]; ADD[9] = SX[7] & SY[11];
				           DATA=ADD[9:0];m=1;
				     end
				  15:begin ADD[0] = SX[8] & SY[11]; ADD[1] = SX[9] & SY[11]; 
				           ADD[2] = SX[10] & SY[11];ADD[3] = SX[11] & SY[11];
				           ADD[4] = SZ[0] ; ADD[5] = SZ[1] ; ADD[6] = SZ[2] ;
				           ADD[7] = SZ[3] ; ADD[8] = SZ[4] ; ADD[9] = SZ[5] ;
				           DATA=ADD[9:0];m=2;
				    end
			      default: begin DATA=0;m=1;end	
			    endcase
			   end						
			2: begin STATUS=1'b0;DATA=10'b0000000000;cnt=5'b00000;m=3;end
			3: begin STATUS=1'b0;DATA=10'b1111111111;m=1;end
	  default: begin STATUS=1'b0;DATA=10'b0011001100;end
		endcase
	end
end
endmodule