📄 iisnew.c
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(g_oI2SState.BitperCh == 24)?32 : 16;
g_oI2SState.pcmsize = g_oI2SState.SyncClkFreq*g_oI2SState.Totch*fifobyteperch*g_oI2SState.recordSec/8;
if(dummybytesize> (0x33000000-0x32200000) )
{
dummybytesize = 0x33000000-0x32200000;
printf("pcm size is adjusted for converting");
}
if(g_oI2SState.BitperCh == 16)//16->fifo 24bit.
{
PCM_ContinuousPCM2FifoFormat_converting(0x32200000, &g_oI2SState.pcmsize, g_oI2SState.BitperCh,
pcmdataaddr, dummybytesize, dummybitperch);//8 bit not supported
PCM_Resampling(0x32200000, &g_oI2SState.pcmsize, g_oI2SState.SyncClkFreq,
0x32200000, g_oI2SState.pcmsize, dummysamplerate, g_oI2SState.BitperCh) ;
PCM_DATA_2chexpanding(PCM_TESTPLAYINGDATA_BASE, g_oI2SState.Totch, &g_oI2SState.pcmsize,
0x32200000, 2, g_oI2SState.pcmsize, g_oI2SState.BitperCh);
}
else if(g_oI2SState.BitperCh == 8)
{
PCM_Resampling(0x32200000, &g_oI2SState.pcmsize, g_oI2SState.SyncClkFreq,
PCM_TESTPLAYINGDATA_BASE, dummybytesize, dummysamplerate, g_oI2SState.BitperCh) ;
//if same sample rate return, then copy
if(dummysamplerate == g_oI2SState.SyncClkFreq)
memcpy( (void *) 0x32200000, (void *)PCM_TESTPLAYINGDATA_BASE, dummybytesize);//dest, org, bytesize
PCM_DATA_2chexpanding(PCM_TESTPLAYINGDATA_BASE, g_oI2SState.Totch, &g_oI2SState.pcmsize,
0x32200000, 2, g_oI2SState.pcmsize, g_oI2SState.BitperCh);
}
//PCM_DATA_masking( PCM_TESTPLAYINGDATA_BASE, g_oI2SState.pcmsize, g_oI2SState.BitperCh, g_oI2SState.Totch, g_oI2SState.maskingch );
}
extern float IIS_Codec_CLK;
// I2S_PLAY( ePort,
// rec_buff, 464000,
// tx, i2sformat, 384fs, 16bit
// );//port, source, setting,
////(iCDCLKCON<12)|(iIMS<<10)| is selected at clock select routine. IISMOD[12:10]
//where iIMS = (masterslave<<1 | ipclki2sclk)
//interrupt enable part is selected outside IISCON[17:16]
bool I2S_Setting(int port, int MasterSlave,
int trx, int i2sformat, int rootfs, int bitclkfs, int ch, int bit, int DmaPolling)
{
int iRFS_LRCLK=0, iBFS_BCLK=0, iBLC=0, iDCE=0;
int iTXR=0, iLRP=0, iSDF=0;
//trx
iTXR = (0<=trx && trx<3)? trx : -1;
//data format
iSDF = (-1<i2sformat && i2sformat<3)? i2sformat : -1;
iLRP = (i2sformat==0)?0:1;//left is lrclk low at i2s mode, left is lrclk high at msb, lsb mode
//roofs
iRFS_LRCLK = (rootfs == 256)? 0 :
(rootfs == 512)? 1 :
(rootfs == 384)? 2 :
(rootfs == 768)? 3 : -1;
printf("\n Root Frequency Sample ( 0:256fs 1:512fs 2:384fs 3:768fs ) = %d", iRFS_LRCLK);
//ch
iDCE = (ch == 2)? 0 :
(ch == 4)? 1 :
(ch == 6)? 3 : -1;
printf("\n DCE(ch) (0: 2ch 1:2ch+2ch0 2: 2ch+2ch1 3: 2ch+2ch0+2ch1) = %d", iDCE);
//bit
iBFS_BCLK = (bitclkfs == 32)? 0 :
(bitclkfs == 48)? 1 :
(bitclkfs == 16)? 0 :
(bitclkfs == 24)? 3 : -1;
printf("\n Bit Frequency Sample (0:32fs 1:48fs 2:16fs 3:24fs) = %d", iBFS_BCLK);
iBLC = (bit == 16)? 0 :
(bit == 8)? 1 :
(bit == 24)? 2 : -1;
printf("\n BLC (0: 16bit 1:8bit 2: 24bit) = %d", iBLC);
if(MasterSlave != I2S_MASTER)
{
iBFS_BCLK=0;//in slave it determined by clock input
iRFS_LRCLK=0;
}
//assert
if(iTXR<0 || iSDF<0) return 0;
if(iRFS_LRCLK <0 || iBFS_BCLK<0 || iBLC <0 || iDCE<0) return 0;
if( port == I2S_PORT0)
{
//fifo control
if(iTXR == I2S_MODE_TX || iTXR == I2S_MODE_TXR)
{
rIISFIC = 0+(1<<15);
rIISFIC = 0+(0<<15);
}
if(iTXR == I2S_MODE_RX || iTXR == I2S_MODE_TXR)
{
rIISFIC = (1<<7) + 0; // jungil
rIISFIC = (0<<7) + 0; // jungil
}
//Interface mode : CDCLKCON[12], IMS[11:10] should be set prior to this.
rIISMOD = rIISMOD & ~(0x3fe3ff) |(iDCE<<16)|(iBLC<<13)| (iTXR<<8)|(iLRP<<7)|(iSDF<<5)|(iRFS_LRCLK<<3)|(iBFS_BCLK<<1);
printf("rIISMOD =0x%x", rIISMOD);
//dma transfer mode setting
if(DmaPolling == I2S_DMA)
{
if(iTXR == I2S_MODE_TX)
rIISCON = rIISCON & ~(0x7f) | (0<<6) | (1<<5) | (0<<4) | (1<<3) | (1<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:N, rxdma:Y, txch:N, rxch:Y | txdma:Y, rxdma:N, i2s:N
else if(iTXR == I2S_MODE_RX)
rIISCON = rIISCON & ~(0x7f) | (1<<6) | (0<<5) | (1<<4) | (0<<3) | (0<<2) | (1<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:N, txch:Y, rxch:N | txdma:N, rxdma:Y, i2s:N
else
rIISCON = rIISCON & ~(0x7f) | (0<<6) | (0<<5) | (0<<4) | (0<<3) | (1<<2) | (1<<1) | 0;// this setting for TX RX Simulateously
//PAUSE(6:3], ACTIVE[2:0]- txdma:N, rxdma:N, txch:N, rxch:N | txdma:N, rxdma:N, i2s:N
}
else
{
if(iTXR == I2S_MODE_TX)
rIISCON = rIISCON & ~(0x7f) | (1<<6) | (1<<5) | (0<<4) | (1<<3) | (0<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:Y, txch:N, rxch:Y | txdma:N, rxdma:N, i2s:N
else if(iTXR == I2S_MODE_RX)
rIISCON = rIISCON & ~(0x7f) | (1<<6) | (1<<5) | (1<<4) | (0<<3) | (0<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:Y, txch:Y, rxch:N | txdma:N, rxdma:N, i2s:N
else
rIISCON = rIISCON & ~(0x7f) | (1<<6) | (1<<5) | (0<<4) | (0<<3) | (0<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:Y, txch:N, rxch:N | txdma:N, rxdma:N, i2s:N
}
}
else
{
//fifo control
if(iTXR == I2S_MODE_TX || iTXR == I2S_MODE_TXR)
{
rIISFIC1 = 0+(1<<15);
rIISFIC1 = 0+(0<<15);
}
if(iTXR == I2S_MODE_RX || iTXR == I2S_MODE_TXR)
{
rIISFIC1 = (1<<7) + 0; // jungil
rIISFIC1 = (0<<7) + 0; // jungil
}
//Interface mode : CDCLKCON[12], IMS[11:10] should be set prior to this.
rIISMOD1 = rIISMOD1 & ~(0x63ff) |(iBLC<<13)|(iTXR<<8)|(iLRP<<7)|(iSDF<<5)|(iRFS_LRCLK<<3)|(iBFS_BCLK<<1);
printf("rIISMOD1 =0x%x", rIISMOD1);
//dma transfer mode setting
if(DmaPolling == I2S_DMA)
{
if(iTXR == I2S_MODE_TX)
rIISCON1 = rIISCON1 & ~(0x7f) | (0<<6) | (1<<5) | (0<<4) | (1<<3) | (1<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:N, rxdma:Y, txch:N, rxch:Y | txdma:Y, rxdma:N, i2s:N
else if(iTXR == I2S_MODE_RX)
rIISCON1 = rIISCON1 & ~(0x7f) | (1<<6) | (0<<5) | (1<<4) | (0<<3) | (0<<2) | (1<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:N, txch:Y, rxch:N | txdma:N, rxdma:Y, i2s:N
else
rIISCON1 = rIISCON1 & ~(0x7f) | (0<<6) | (0<<5) | (0<<4) | (0<<3) | (1<<2) | (1<<1) | 0;// this setting for TX RX Simulateously
//PAUSE(6:3], ACTIVE[2:0]- txdma:N, rxdma:N, txch:N, rxch:N | txdma:N, rxdma:N, i2s:N
}
else
{
if(iTXR == I2S_MODE_TX)
rIISCON1 = rIISCON1 & ~(0x7f) | (1<<6) | (1<<5) | (0<<4) | (1<<3) | (0<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:Y, txch:N, rxch:Y | txdma:N, rxdma:N, i2s:N
else if(iTXR == I2S_MODE_RX)
rIISCON1 = rIISCON1 & ~(0x7f) | (1<<6) | (1<<5) | (1<<4) | (0<<3) | (0<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:Y, txch:Y, rxch:N | txdma:N, rxdma:N, i2s:N
else
rIISCON1 = rIISCON1 & ~(0x7f) | (1<<6) | (1<<5) | (0<<4) | (0<<3) | (0<<2) | (0<<1) | 0;
//PAUSE(6:3], ACTIVE[2:0]- txdma:Y, rxdma:Y, txch:N, rxch:N | txdma:N, rxdma:N, i2s:N
}
}
printf("\nIISLRCK = %d Hz", (int) IIS_Codec_CLK/rootfs);
return 1;
}
//default setting :
// codec WM8580
// master
// PCLK(XTAL) 12Mhz
// codec clock 16.934Mhz
// 44000Hz
// 384fs
// DMA
// tx
// i2s format
// 2ch
//select :
// port
// 16,24,8bit
// source address, sourcesize
//before starting playing pcm data should be inserted at 0x31000000
//by
//DownloadData();
//PCM_DATA_2chpattern_making( 0x31000000, 500000/5000,5000, 16);
//destaddr, unit repeat datasize, repeat num, bitperch
bool I2S_MasterBasicTestSub( int Port,
int dataformat, int bit, int Totch,
unsigned int sourceaddr, unsigned int sourcesize)
{
bool ret;
char ch;
//assert
IIS_Port_Init(Port);
//I2S_PCLK_speed_change(16910, 12000);//fout, fin
//pdf = 0; // prescaler division factor(FPGA) 16.91/(0+1)=16.91Mhz (Default)
//Select_PCLK(0);//44.1Khz
//Select_PCLK(1);//22.05Khz
Select_EPLL(Port, 0);
//before starting playing pcm data should be inserted at 0x31000000
//2450
ret=I2SCODEC_InitWm8580(I2S_MASTER,
//I2S_MODE_TX, I2S_FORMAT_I2S, 0, BitperCh);
I2S_MODE_TX, dataformat, 0, bit);
//int OpMode,
//int txr, int dataformat, int CodecClkFs, int BitperCh)
if(!ret) return 0;
if(sourceaddr>0 && sourcesize>0)
{
//I2S_Setting(Port, 0, 0, 384, 2, BitperCh);
I2S_Setting(Port, I2S_MASTER, I2S_MODE_TX, dataformat, 384, bit*2, Totch, bit, I2S_DMA);
//Port, int trx, int i2sformat, int rootfs, int ch, int bit);
IIS_PlayWave_DMA( Port, (unsigned char *)sourceaddr, sourcesize, bit);//0x31000000, 500000);
}
// need to add mute function
IIS_Port_Return(Port);
return 1;
}
//for bigger than 4mega byte, in dma mode autoreload should be considered.
//in polling mode it may not be needed.
bool PCM_testpatternmemcopy(unsigned int testaddr, unsigned char totch, unsigned char bitperch)
{
bool bret=0;
unsigned int destsizeByte;
//assert
if(testaddr==0) return 0;
if(totch>6) return 0;
if(bitperch>24) return 0;
//2ch fifo compatiable pattern making
printf("test source is test pattern\n");
printf("be careful, do not listen by speaker, headset, testpattern is harmful for your ear!!!\n");
printf("just check I2S0 link additional TP45 SDO_0 TP46 SDO_1 by logic analyzer \n" );
bret =PCM_DATA_2chpattern_making( &destsizeByte,
// (unsigned int)(PCM_TESTPATTERN_ORG_BASE+4), (unsigned int)2,4400, bit);//24bit 6ch not work
// (unsigned int)(PCM_TESTPATTERN_ORG_BASE+4), (unsigned int)1,4400, bit);//work
(unsigned int)(PCM_TESTPATTERN_ORG_BASE+4), (unsigned int)6,4400, bitperch);//16 bit 6ch not work
if(bret==0) return 0;
*(unsigned int* )(PCM_TESTPATTERN_ORG_BASE) = destsizeByte;
//expanding
PCM_DATA_2chexpanding(testaddr, totch, &destsizeByte,
PCM_TESTPATTERN_ORG_BASE+4, 2, destsizeByte, bitperch);
return 1;
}
//with default setting check all with clock source selection playing are ok
// master : i2s0
// slave : wm8580
// PCLK(XTAL), 12Mhz,
// codec clock 16.934Mhz 44000Hz, 384fs,DMA, tx, i2s format,
//pcm
//port, totch, bit are input variable
//test pattern / or test pcm is located in 0x32200000
//testsource 0: pattern 1:32bit 2ch 44000Hz pcmfile
bool I2S_ChannelTest(int testsource, int port, int dataformat, int totch, int bit, int maskingch, bool testsourceredownload)
{
int failnum;
bool bret=0;
unsigned int destsizeByte;
unsigned int orgsize;
if(testsourceredownload)
{
printf("please set om[0] hardware pin to 0, and XTAL is installed with 12Mhz\n");
printf("if not, please turn off board, set, then restart this test\n");
if(testsource ==1)
{
printf("test source is pcm file\n");
orgsize=PCM_TestSourceDownload(PCM_WAVEFILE_ORG_BASE, "please download 44000Hz 32bit 2ch stereo Wave pcm file\n");
orgsize = (orgsize>0x2c)? (orgsize-0x2c) : 0;
PCM_ContinuousPCM2FifoFormat_converting(PCM_TEMPORARILY_CONVERTING_BASE+4, &destsizeByte, bit,
PCM_WAVEFILE_ORG_BASE+4+0x2c, orgsize, 32);
//unsigned int destaddr, unsigned int* destsize, int destbit,
//unsigned int orgaddr, int orgsize, int orgbit);
*(unsigned int* )(PCM_TEMPORARILY_CONVERTING_BASE) = destsizeByte;
}
else
{
printf("test source is test pattern\n");
printf("be careful, do not listen by speaker, headset, testpattern is harmful for your ear!!!\n");
printf("just check I2S0 link additional TP45 SDO_0 TP46 SDO_1 by logic analyzer \n" );
bret =PCM_DATA_2chpattern_making( &destsizeByte,
// (unsigned int)(PCM_TESTPATTERN_ORG_BASE+4), (unsigned int)2,4400, bit);//24bit 6ch not work
// (unsigned int)(PCM_TESTPATTERN_ORG_BASE+4), (unsigned int)1,4400, bit);//work
(unsigned int)(PCM_TESTPATTERN_ORG_BASE+4), (unsigned int)6,4400, bit);//16 bit 6ch not work
if(bret==0) return 0;
*(unsigned int* )(PCM_TESTPATTERN_ORG_BASE) = destsizeByte;
}
}
else
{
if(testsource==1)
destsizeByte = *(unsigned int* )(PCM_TEMPORARILY_CONVERTING_BASE);
else
destsizeByte = *(unsigned int* )(PCM_TESTPATTERN_ORG_BASE);
}
if(testsource == 1)
PCM_DATA_2chexpanding(PCM_TESTPLAYINGDATA_BASE, totch, &destsizeByte,
PCM_TEMPORARILY_CONVERTING_BASE+4, 2 , destsizeByte, bit);
//unsigned int destaddr, int destTotch, unsinged int* destsize
//unsigned int orgaddr , int orgTotch, int orgBit, unsigned int orgsize
else
PCM_DATA_2chexpanding(PCM_TESTPLAYINGDATA_BASE, totch, &destsizeByte,
PCM_TESTPATTERN_ORG_BASE+4, 2, destsizeByte, bit);
PCM_DATA_masking( PCM_TESTPLAYINGDATA_BASE, destsizeByte, bit, totch, maskingch );
//unsigned int destaddr, int datasize, int bit, int Totalch, int maskingch
bret=I2S_MasterBasicTestSub(port, dataformat, bit, totch,
PCM_TESTPLAYINGDATA_BASE, destsizeByte);
//int Port, int bit, int Totch,
//unsigned int sourceaddr, unsigned int sourcesize)
return bret;
}
//end of file⌨️ 快捷键说明
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