iisnew.c

samsung 最新芯片2450 的测试程序.

	i= GetIntNum();
	if(i==1)
		g_oI2SState.Dataformat= I2S_FORMAT_MSB;	
	else if(i==2)
		g_oI2SState.Dataformat= I2S_FORMAT_LSB;
	else if(i==3)
		g_oI2SState.Dataformat= I2S_FORMAT_NOP;	
	else 
		g_oI2SState.Dataformat = I2S_FORMAT_I2S;//default
}

void I2S_Select_dmapolling(void)
{
	int i;
	printf("Select I2S service mode : 0. DMA-sinle[D]  1. Polling");
	i= GetIntNum();
	if(i==1)
		g_oI2SState.DmaPolling= I2S_POLLING;
	else 
		g_oI2SState.DmaPolling = I2S_DMA;//default
}

void I2S_en_underrunINT(void)
{
	int i;
	printf("Select Underrun Interrupt 0. Enalbe[D]  1. Disable");
	i= GetIntNum();
	if(i==1)
		g_oI2SState.benUnderInt=0;
	else 
		g_oI2SState.benUnderInt=1;//default
}


void I2S_en_24bittest(void)
{
	int i;
	printf("Select 24bit Underrun/overrun test mode 0. Enalbe[D]  1. Disable");
	i= GetIntNum();
	if(i==1)
		g_oI2SState.ben24bittest=0;
	else 
		g_oI2SState.ben24bittest=1;//default
}



/////////////////////////////////////////////////////
// Master Clock setting
/////////////////////////////////////////////////////
//get input when sel is -1
//else use input value

//return selectedclk source 0 pclk, 1. extclk,epll, epll ref
unsigned char Select_IIS_Master_CLK(int sel)
{
	//int sel;
	//unsigned short Sampling_Rate;
	
	
	
    printf("\nSelect IIS Master Clock Source\n");
	printf("0:PCLK, 1:IIS EXTCLK, 2:EPLL[D], 3:EPLL Ref. CLK :");
	
	if(sel == -1) sel = GetIntNum();		
	
	switch(sel)
	{
		case 0://In case of IIS Master Clock Source = PCLK
		//I2S_PCLK_speed_change(16910,12000);//fout, fin
		Select_PCLK(g_oI2SState.Port, 4-1);
		break;

		case 1://In case of IIS Master Clock Source = EXTCLK Form GPIO (CDCLK input)
		Select_EXTCLK(g_oI2SState.Port, 0);
		break;

		case 3://In case of IIS Master Clock Source = EPLL Ref. CLK
		Select_EPLL_Ref_CLK(g_oI2SState.Port, 0);
		break;

		default://In case of IIS Master Clock Source = divided EPLL or EPLL ref.
		Select_EPLL(g_oI2SState.Port, 0);
		break;
	}
	
	if(sel>0 && sel<4) return 1;
	else return 0;
}




//epllclksource : 10 XTAL[d] 11 EXTCLK 0x same with mpll om setting
//fin, fout (Hz)
//return : 1: success, 0 : fail
//recommanded error ratio : fill here.
bool EPLL_speed_change(unsigned int fin, unsigned int fout)
{
	//esysclk source select	
		rCLKSRC = (rCLKSRC & ~(1<<6)) | (1<<6); //   ESYSCLK Soure is divided EPlL clock
			     //1d0

	//speed setting	
		//2443 setting										
			//rEPLLCON= (40<<16) | (1<<8) | 1;	// EPLL OUT IS 96Mhz   : (Mdiv<<16) | (Pdiv<<8) | Sdiv;	
		//2450 fpga io bd, use same emulation pll with mpll (fout = fin*m /(p*2s) , fin = 16.9344 EXTCLK
			//rEPLLCON= (20<<16) | (10<<8) | 1;	// EPLL OUT IS 16.9344Mhz   : (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
		//2450 fpga io bd, use same emulation pll with mpll (fout = fin*m /(p*2s) , fin = 12 XTAL
			//rEPLLCON= (31<<16) | (11<<8) | 1;//16.91Mhz (m*Fin)/(p*2s), , Fin 12Mhz	
		if(fin ==	12000000)
		{
			switch(fout)
			{
			//case 	16934400:			
			//	rEPLLCON= (31<<16) | (11<<8) | 1;//16.91Mhz (m*Fin)/(p*2s), , Fin 12Mhz
			//break;
			
			case  	406425600:			
				rEPLLCON= (33<<16) | (1<<8) | 0;//16.91Mhz (m*Fin)/(p*2s), , Fin 12Mhz
				rEPLLCON_K = 56938;
			break;
			
			case 	589824000:			
				rEPLLCON= (49<<16) | (1<<8) | 0;//16.91Mhz (m*Fin)/(p*2s), , Fin 12Mhz
				rEPLLCON_K = 9961;
			break;						
			
			default:
				return 0;
			}			
		}
		else
		if(fin== 	16934400)
		{
			switch(fout)
			{
			//case 	16934400:			
			//	rEPLLCON= (20<<16) | (10<<8) | 1;	// 16.9344Mhz   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
			//break;
			case 	36864000://0.4%			
				rEPLLCON= (13<<16) | (3<<8) | 1;	// 36.864Mhz   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
			break;
			
			case 	33868800://V
				rEPLLCON= (12<<16) | (3<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
			break;

			case 	24576000://0.08%
				rEPLLCON= (29<<16) | (10<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
			break;

			case 	22579000://1.13%
				rEPLLCON= (29<16) | (11<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
			break;

			case 	16384000://0.086%
				rEPLLCON= (29<<16) | (15<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 16.9344
			break;

			
			default:
				return 0;
			}
		}
		else
		if(fin == 32768000)
		{
			switch(fout)
			{
			case 	36864000://V			
				rEPLLCON= (9<<16) | (4<<8) | 1;	// 36.864Mhz   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 32.768
						//0x90401
			break;
			
			case 	33868800://0.02%
				rEPLLCON= (31<<16) | (5<<8) | 3;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 32.768			
			break;

			case 	24576000://V
				rEPLLCON= (6<<16) | (4<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 32.768			
			break;

			case 	22579000://0.22%
				rEPLLCON= (11<<16) | (8<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 32.768			
			break;

			case 	16384000:
				rEPLLCON= (8<<16) | (8<<8) | 1;//   (m*Fin)/(p*2s): (Mdiv<<16) | (Pdiv<<8) | Sdiv;	fin is 32.768			
			break;

			
			default:
				return 0;
			}			
		}
		Delay(100);

	//epll monitor
		rGPHCON = (rGPHCON & ~(3<<28)) | (2<<28);//clkout1(tp 32)
		rMISCCR = (rMISCCR & ~(7<<8))  | (1<<8);//gated epll? output
		printf("Check EPLL OUT(TP5 for 2450 smdk io b'd!! and  Press Ant Key if You Want Go!!\n");
		//getchar();	

	return 1;
}

//unit Khz
void I2S_PCLK_speed_change(int fout, int fin)
{

	//assert


	//common-prior
	rGPACON = rGPACON& ~(1<<10);//RDATA_OEN enable

	PreChangeSDRAMParameter();
	
	rGPHCON=rGPHCON&~(0xf<<26)|(0xa<<26); //CLKOUT0,1
	rMISCCR=rMISCCR&~((0x7<<8)|(0x7<<4))|(0x3<<8)|(0x2<<4); //HCLK,ARMCLK

	if(fin == 12000)
	{
		switch(fout)
		{
		
		case 33600:
			SetCLKDIV( 0, 0, 0, 0); // 1:1:1		//not allowed
			Delay(10); 
			SetMPLL( 28, 5, 1);		// 33.6Mhz (m*Fin)/(p*2s) , Fin 12Mhz		
		break;
		

		case 16910:
			SetMPLL( 31, 11, 1);		// 16.91Mhz (m*Fin)/(p*2s), , Fin 12Mhz
			Delay(10); 
			SetCLKDIV( 0, 0, 0, 0); // 1:1:1		
			Delay(10); 
			SetMPLL( 31, 11, 1);		//16.91Mhz (m*Fin)/(p*2s), , Fin 12Mhz
		break;		
		}
		
	}
	else 
	if(fin == 16934)
	{
		switch(fout)
		{
		
		case 16934:
			SetCLKDIV( 0, 0, 0, 0); // 1:1:1		
			Delay(10); 
			SetMPLL( 20, 10, 1);		// 16.91Mhz (m*Fin)/(p*2s), , Fin 16.9344Mhz
		break;		
		}
		
	}
	
	//common-after
	rCLKSRC	=	(rCLKSRC) | (1<<4);
	SystemCLK(0);
	ChangeSDRAMParameter(HCLK);
	Delay(10);
		
	Max1718_Init();
	Isr_Init();
	MMU_Init();
	Delay(0); //calibrate Delay()
	
	Console(1);
}


//////////////////////////////////////////////////////////////////////
//preload by trace32 @32c00000 24bit file
//tot ch should be set outside of it.
//g_oI2SState.SyncClkFreq also 
//setting is done
void I2S_Testdataprepare()
{
	unsigned short dummytotch;
	unsigned int 	dummysamplerate;
	unsigned short 	dummybitperch;
	
	unsigned int	pcmdataaddr;

	I2S_selectBit();
	I2S_selectSyncFreq();
	I2S_Select_Totch();
	I2S_Select_ChannelMask();

	
	if(g_oI2SState.SyncClkFreq % 4000 == 0)		
		PCM_waveparser(0x32c00000,
						&dummytotch,
						&dummysamplerate,
						&dummybitperch,
						&g_oI2SState.pcmsize,
						&pcmdataaddr
						);	
	else
		PCM_waveparser(0x32800000,
						&dummytotch,
						&dummysamplerate,
						&dummybitperch,
						&g_oI2SState.pcmsize,
						&pcmdataaddr
						);
						
	PCM_ContinuousPCM2FifoFormat_converting(0x32200000, &g_oI2SState.pcmsize, g_oI2SState.BitperCh,
							   pcmdataaddr, g_oI2SState.pcmsize, dummybitperch);//0x2c-16bit, 0x44 32bit - goldwave format.
	PCM_Resampling(0x32200000, &g_oI2SState.pcmsize, g_oI2SState.SyncClkFreq,
				   0x32200000,  g_oI2SState.pcmsize, dummysamplerate, g_oI2SState.BitperCh)	;
	PCM_DATA_2chexpanding(PCM_TESTPLAYINGDATA_BASE, g_oI2SState.Totch, &g_oI2SState.pcmsize,
					   	  0x32200000, 2, 	 			  g_oI2SState.pcmsize, g_oI2SState.BitperCh);						   
	PCM_DATA_masking( PCM_TESTPLAYINGDATA_BASE, g_oI2SState.pcmsize, g_oI2SState.BitperCh, g_oI2SState.Totch, g_oI2SState.maskingch );
}





//preload by trace32 @32000000 16bit file -> 31000000 24bit converting
//setting is done
void I2S_Testdataprepare3()
{
	unsigned int	pcmdataaddr;
	PCM_waveparser(0x32000000,
					&g_oI2SState.Totch,
					&g_oI2SState.SyncClkFreq,
					&g_oI2SState.BitperCh,
					&g_oI2SState.pcmsize,
					&pcmdataaddr
					);
	PCM_ContinuousPCM2FifoFormat_converting(PCM_TESTPLAYINGDATA_BASE, &g_oI2SState.pcmsize, 24,
							   pcmdataaddr, g_oI2SState.pcmsize, g_oI2SState.BitperCh);
	g_oI2SState.BitperCh=24;
}

//preload by trace32 @31000000 32bit file -> 31000000 24bit converting
//setting is done
void I2S_Testdataprepare4()
{
	unsigned int	pcmdataaddr;
	PCM_waveparser(0x31000000-0x50,
					&g_oI2SState.Totch,
					&g_oI2SState.SyncClkFreq,
					&g_oI2SState.BitperCh,
					&g_oI2SState.pcmsize,
					&pcmdataaddr
					);
	PCM_ContinuousPCM2FifoFormat_converting(PCM_TESTPLAYINGDATA_BASE, &g_oI2SState.pcmsize, 24,
							   pcmdataaddr, g_oI2SState.pcmsize, g_oI2SState.BitperCh);
	g_oI2SState.BitperCh=24;
}


//convert recorded data to own format.
//expanding is possible. 
void I2S_Testdataprepare2()
{
	unsigned short dummytotch;
	unsigned int 	dummysamplerate;
	unsigned short 	dummybitperch;	
	unsigned int	pcmdataaddr;	
	unsigned int	dummysec;
	unsigned int dummybytesize;	
	unsigned int fifobyteperch;
	
	//recored setting
	pcmdataaddr=PCM_TESTPLAYINGDATA_BASE;
	dummysamplerate=g_oI2SState.SyncClkFreq;
	dummybitperch=g_oI2SState.BitperCh;
	fifobyteperch = (g_oI2SState.BitperCh == 8)? 16 : 
				   (g_oI2SState.BitperCh == 24)?32 : 16;
	
	dummybytesize = dummysamplerate*dummytotch*fifobyteperch*g_oI2SState.recordSec/8;	
	dummytotch = 2;
	
	I2S_selectBit();
	I2S_selectSyncFreq();
	I2S_Select_Totch();
	I2S_Select_ChannelMask();	
	fifobyteperch = (g_oI2SState.BitperCh == 8)? 16 :