iis.c

samsung 最新芯片2450 的测试程序.

		bLRCLKold = bLRCLK; bSCLKold=bSCLK;
		
		i++;
		
		if(i>0x100000) break;
	}
	
	if(cntLRtoggle>20 && cntSCLKtoggle>20) bret = 1;

	printf("LRCLK toggle :%d, SCLK toggle:%d\n", cntLRtoggle, cntSCLKtoggle);
	if(!bret)
	{
		printf("CAUTION : Slave Clock is not feeding from Master\n");
		if(cntLRtoggle<=20) printf("LRCLK is not from Master\n");
		if(cntSCLKtoggle<=20) printf("SCLK is not from Master\n");
	}
	else
		printf("OK : Slave Clock is feeding from Master\n");

	return bret;
}

void I2S_Slave_ClockinTest(int port, int MasterSlave)
{
	bool bret;

	if(MasterSlave == I2S_MASTER) return;

	I2S_SetToGPIO(port);//set sclk, lrclk to input
	
	//monitoring, toggle detect
	bret=I2S_ClockTEST(port);
	
	IIS_Port_Init();//restore to i2s gpio
	
}

void IIS_Port_Return()
{
	if(g_oI2SState.Port == I2S_PORT0)
	{
	 	rGPECON = save_GPE_CON;	// IIC, IIS
		rGPESEL = save_GPE_SEL;	// IIC, IIS
		rGPEUDP = save_GPE_UDP;	// IIC, IIS
		
		rGPBSEL = save_GPB_SEL;	// IIS
		rGPBUDP = save_GPB_UDP;	// IIS	
		
	}
	else
	{
		rGPLCON = save_GPL_CON;	// IIS1
		rGPLSEL = save_GPL_SEL;	// IIS1
		rGPLUDP = save_GPL_UDP;	// IIS1
		
		rGPJCON = save_GPJ_CON;	// IIS1
		rGPJSEL = save_GPJ_SEL;	// IIS1
		rGPJUDP = save_GPJ_UDP;	// IIS1				
	}

}





// IIS source clock selection
//pdf = 3; // prescaler division factor(SMDK) 66/(3+1)=16.5Mhz
//pdf = 1; // prescaler division factor(FPGA) 16.91/(1+1)=8.34Mhz
//pdf = 0; // prescaler division factor(FPGA) 16.91/(1+0)=16.91Mhz
void Select_PCLK(int port, unsigned int pdf)
{

	if(port == I2S_PORT0)
	{
		// SYSCON register setting
		rPCLKCON |= (1<<9); // PCLK bus block of i2s enable
		//rSCLKCON |= (1<<9); // I2S source clock enable
		
		// IIS clock register setting
		rIISMOD = (rIISMOD & ~(7<<10)) | (0<<12)|(0<<10); // internal codec clock source, PCLK Master mode
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]
		
		//2450
		rIISPSR = (1<<15)|(pdf<<8);  // prescaler enable, prescaler division factor[13:8]
	}
	else
	{
		// SYSCON register setting
		rPCLKCON |= (1<<17); // PCLK bus block of i2s enable
		//rSCLKCON |= (1<<5); // I2S source clock enable
		
		// IIS clock register setting
		rIISMOD1 = (rIISMOD1 & ~(7<<10)) | (0<<12)|(0<<10); // internal codec clock source, PCLK Master mode
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]
		
		//2450
		rIISPSR1 = (1<<15)|(pdf<<8);  // prescaler enable, prescaler division factor[13:8]
		
	}
			
	//In case PCLK = 50 MHz, IIS Codec CLK = 50/(5+1) = 8.34MHz-->22KHz (SMDK)
	//In case PCLK = 16.91 MHz, IIS Codec CLK = 16.91/(1+1) = 8.455MHz-->22KHz (FPGA)
	//In case PCLK = 16.91 MHz, IIS Codec CLK = 16.91/(0+1) = 16.91MHz-->44KHz (FPGA)
	printf("\nIIS Master CLK(PCLK) = %4.2f MHz", (float)PCLK/1000000);
	IIS_Codec_CLK = (float)PCLK/(pdf+1);
	printf("\nIIS Codec CLK = %4.2f MHz", IIS_Codec_CLK/1000000);

}

//pdf = 0; // prescaler division factor
void Select_EXTCLK(int port, unsigned int pdf)
{
	printf("\n Board To Board Test Source Board is OK? \n");
	
	if(port == I2S_PORT0)
	{
		// Clock gating 
		rPCLKCON = (rPCLKCON & ~(1<<9)) | (1<<9); // PCLK bus block of i2s enable
		rSCLKCON |= (1<<9); // I2S source clock enable
	
		//i2s source clock select / clkdiv1 setting		
		rCLKSRC = (rCLKSRC & ~(3<<14)) | (1<<14); // I2S first source clock selection external clock
		//rCLKDIV1 &= ~(0xf<<12);	// I2S clock divider for EPLL.
	
		// IIS clock register setting
		rIISMOD = (rIISMOD & ~(7<<10)) | (1<<12)|(1<<10); // Get Codec clock from extenal codec chip, using codeclki master mode
		
		//2443
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]		
		//2450
		rIISPSR = (1<<15)|(pdf<<8);  // prescaler enable, prescaler division factor[13:8]
	}
	else
	{
		// clock gating
		rPCLKCON = (rPCLKCON & ~(1<<17)) | (1<<17); // PCLK bus block of i2s enable
		rSCLKCON |= (1<<5); // I2S source clock enable		
		
		rCLKSRC = (rCLKSRC & ~(3<<12)) | (1<<12); // I2S source clock selection external clock
		//rCLKDIV2 &= ~(0xf<<12);	// I2S clock divider for EPLL.
		
		// IIS clock register setting
		rIISMOD1 = (rIISMOD1 & ~(7<<10)) | (1<<12)|(1<<10); // Get Codec clock from extenal codec chip, using codeclki(i2s clock) master mode

		//2443
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]		
		//2450
		rIISPSR1 = (1<<15)|(pdf<<8);  // prescaler enable, prescaler division factor[13:8]			
	}
			
}


//epll ref clock source select among xtal and extclk(if installed)
void EPLL_setEPLLREF_Source(int epllrefsource)
{
	unsigned char SELESRC;	
	int i;
	
	printf("select epll clk source:0.as in OM[0] 1. as in OM[0] 2. XTAL[D]  3. EXTCLK\n");
	printf("choose:");	
	if(epllrefsource<0) i=GetIntNum();
	else i = epllrefsource;//^^:
	
	SELESRC = ( i==0)?0:
					( i==1)?1:
					( i==3)?3:2;	
					
	rCLKSRC = (rCLKSRC & ~(3<<7)) | (SELESRC<<7);
}


//pdf = 0; // prescaler division factor(FPGA) 16.91/(1+0)=16.91Mhz
// pdf : do not use at smdk.
//return : 1 success, 0 fail
// clock path : 
// epll out -> i2sdiv ->   select ->  prescaler  ->cdclk.
//                     |           |
//                   clockaudio    i2s clk
bool Select_EPLL(int port, unsigned int pdf)
{
	//unsigned int pdf = 10; // prescaler division factor
	bool bret;
	unsigned int fin, fout, parentclk;
	int i;
	unsigned int ipdf=pdf;
	
	unsigned int eplldiv, prescalerdiv;

	//epll clock source select among xtal and extclk(if installed)
	EPLL_setEPLLREF_Source(2);//xtal	
	
	printf("select input clk speed : 1. 12000000Hz[D] 2. 16934400Hz 3. 32768000Hz\n");
	printf("choose:");
	//i=GetIntNum();
	i = 1;	
	fin= (i==2)? 16934400 : 
		 (i==3)? 32768000 : 12000000;

	printf("select output clk speed : 1. 16934400Hz[D] 2. 36864000Hz  3. 33868800 4. 24576000  5.22579000  6.16384000  \n");
	printf("choose:");
	
	/*i=GetIntNum();
		
	fout= (i==2)? 36864000 :
		  (i==3)? 33868800 :
		  (i==4)? 24576000 :
		  (i==5)? 22579000 :
		  (i==6)? 16384000 : 16934400;
	*/
	
	fout = 	(32768000%g_oI2SState.CDCLKFreq ==0)?589824000 :
			(45158400%g_oI2SState.CDCLKFreq ==0)?406425600 : 
			(49152000%g_oI2SState.CDCLKFreq ==0)?589824000 :
			(33868800%g_oI2SState.CDCLKFreq ==0)?406425600 : 
			(36864000%g_oI2SState.CDCLKFreq ==0)?589824000 : 0;
	
	printf("cdclkfreq : %d Hz, fout : %d Hz \n", g_oI2SState.CDCLKFreq, fout);
	if(fout == 0) return 0;

	//esysclk source select, speed setting
	bret=EPLL_speed_change(fin, fout);
	if(!bret) return 0;
	
	parentclk = (32768000%g_oI2SState.CDCLKFreq ==0)?32768000 :
			(45158400%g_oI2SState.CDCLKFreq ==0)?45158400 : 
			(49152000%g_oI2SState.CDCLKFreq ==0)?49152000 :
			(33868800%g_oI2SState.CDCLKFreq ==0)?33868800 : 
			(36864000%g_oI2SState.CDCLKFreq ==0)?36864000 : 0;


	eplldiv = fout / parentclk; //1~16
	eplldiv = (eplldiv>16)? eplldiv/2 : eplldiv;
	printf("eplldiv : %d\n", eplldiv);
    if(eplldiv > 16) return false;	    
  
	printf("cdclkfreq : %d Hz, fout : %d Hz,  parentclk : %d Hz eplldiv(d) : %d \n",
			 g_oI2SState.CDCLKFreq, fout, parentclk, eplldiv);		
    eplldiv = eplldiv -1;    		

	printf("select i2s prescaler value : \n");
	//printf("enter:");
	//ipdf=GetIntNum();
	
	prescalerdiv = parentclk / g_oI2SState.CDCLKFreq;	
	printf("%d\n", prescalerdiv);
	prescalerdiv = prescalerdiv-1;
	if( prescalerdiv >63) return;
	
	
	if(port == I2S_PORT0)
	{
	// Clock gating 
		rPCLKCON = (rPCLKCON & ~(1<<9)) | (1<<9); // PCLK bus block of i2s enable
		rSCLKCON |= (1<<9); // I2S source clock(epll, epllref, ext) enable		
		
	//i2s source clock select / clkdiv1 setting	
		rCLKSRC = (rCLKSRC & ~(3<<14)) | (0<<14); // I2S source clock selection EPLL divided clock
		rCLKDIV1 = rCLKDIV1 & ~(0xf<<12) | (eplldiv<<12);	// I2S clock divider for EPLL.		
//to test clkdiv1
//rCLKDIV1 = rCLKDIV1 & ~(0xf<<12) | (ipdf<<12);	// I2S clock divider for EPLL.
		
	// IIS clock register setting
		rIISMOD = (rIISMOD & ~(7<<10)) | (0<<12)|(1<<10); // internal codec clock source, EPLL Div Master mode

		//2443
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]		
		//2450
		rIISPSR = (1<<15)|(prescalerdiv<<8);  // prescaler enable, prescaler division factor[13:8]
//rIISPSR = (1<<15)|(0<<8);  // prescaler enable, prescaler division factor[13:8]		

	}
	else
	{
	// clock gating
		rPCLKCON = (rPCLKCON & ~(1<<17)) | (1<<17); // PCLK bus block of i2s enable
		rSCLKCON |= (1<<5); // I2S source clock enable
		
		rCLKSRC = (rCLKSRC & ~(3<<12)) | (0<<12); // I2S source clock selection EPLL divided clock
		rCLKDIV2 = rCLKDIV2 & ~(0xf<<12) | (eplldiv<<12);	// I2S clock divider for EPLL.		
//to test clkdiv2
//rCLKDIV2 = rCLKDIV2 & ~(0xf<<12) | (ipdf<<12);	// I2S clock divider for EPLL.


		
		// IIS clock register setting
		rIISMOD1 = (rIISMOD1 & ~(7<<10)) | (0<<12)|(1<<10); // internal codec clock source, EPLL Div Master mode

		//2443
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]		
		//2450
		rIISPSR1 = (1<<15)|(prescalerdiv<<8);  // prescaler enable, prescaler division factor[13:8]		
//rIISPSR1 = (1<<15)|(0<<8);  // prescaler enable, prescaler division factor[13:8]				
	}
	return 1;
}

//pdf = 1; // prescaler division factor	
void Select_EPLL_Ref_CLK(int port, unsigned int pdf)
{
	//epll clock source select among xtal and extclk(if installed)
	EPLL_setEPLLREF_Source(-1);	
	//esysclk source select	
		//rCLKSRC = (rCLKSRC & ~(1<<6)) | (0<<6); //   ESYSCLK Soure is EPlL reference clock
	//speed setting	
		//rEPLLCON= (1<<24) | (40<<16) | (1<<8) | 1;	// EPLL Off , EPLL OUT IS 96Mhz   : (Mdiv<<16) | (Pdiv<<8) | Sdiv;	

	//epll monitor
		rGPHCON = (rGPHCON & ~(3<<28)) | (2<<28);//clkout1(tp 32)
		rMISCCR = (rMISCCR & ~(7<<8))  | (1<<8);//gated epll? output
		printf("Check EPLL OUT(TP32 for 2450 fpga io b'd!! and  Press Ant Key if You Want Go!!\n");


	if(port == I2S_PORT0)
	{
		// Clock gating 
		rPCLKCON = (rPCLKCON & ~(1<<9)) | (0<<9); // PCLK bus block of i2s disable
		rSCLKCON |= (1<<9); // I2S source clock enable

		//i2s source clock select / clkdiv1 setting	
		printf("set i2s clock source 2. EPLLref 3. EPLLref[D] \n");
		if(GetIntNum() ==2)
			rCLKSRC = (rCLKSRC & ~(3<<14)) | (2<<14); // I2S source clock selection EPLL reference clock
		else
			rCLKSRC = (rCLKSRC & ~(3<<14)) | (3<<14); // I2S source clock selection EPLL reference clock
		//rCLKDIV1 &= ~(0xf<<12);	// I2S clock divider for EPLL.

		Delay(100);
				
		// IIS clock register setting
		rIISMOD = (rIISMOD & ~(7<<10)) | (0<<12)|(1<<10); // internal codec clock source, EPLL Div Master mode


		//2443
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]		
		//2450
		rIISPSR = (1<<15)|(pdf<<8);  // prescaler enable, prescaler division factor[13:8]
	}
	else
	{
	// clock gating
		rPCLKCON = (rPCLKCON & ~(1<<17)) | (0<<17); // PCLK bus block of i2s disable
		rSCLKCON |= (1<<5); // I2S source clock enable
		
		
		printf("set i2s clock source 2. EPLLref 3. EPLLref[D] \n");
		if(GetIntNum() ==2)
			rCLKSRC = (rCLKSRC & ~(3<<12)) | (2<<12); // I2S source clock selection EPLL reference clock	
		else
			rCLKSRC = (rCLKSRC & ~(3<<12)) | (3<<12); // I2S source clock selection EPLL reference clock
		//rCLKDIV2 &= ~(0xf<<12);	// I2S clock divider for EPLL.
		
		// IIS clock register setting
		rIISMOD1 = (rIISMOD1 & ~(7<<10)) | (0<<12)|(1<<10); // internal codec clock source, EPLL Div Master mode

		//2443
		//rIISPSR = (1<<15)|(pdf);  // prescaler enable, prescaler division factor[9:0]		
		//2450
		rIISPSR1 = (1<<15)|(pdf<<8);  // prescaler enable, prescaler division factor[13:8]		
	}

}


//pdf = 1; // prescaler division factor	
void Select_Slave(int port)
{
	int num;

	EPLL_setEPLLREF_Source(-1);	

	if(port == I2S_PORT0)
	{
		// Clock gating 
		rPCLKCON = (rPCLKCON & ~(1<<9)) | (1<<9); // PCLK bus block of i2s enable to operate
		rSCLKCON = (rSCLKCON& ~(1<<9)) | (1<<9); // I2S source clock enable

		//i2s source clock select / clkdiv1 setting	
		printf("set i2s clock source 0. disalbe cdclk out,  2. EPLLref 3. EPLLref[D] \n");
		num = GetIntNum();
		if(  num == 0)
			rSCLKCON = (rSCLKCON& ~(1<<9)) | (0<<9); // I2S source clock disable, cdclk out will be blocked . 
		else if(  num == 2)
			rCLKSRC = (rCLKSRC & ~(3<<14)) | (2<<14); // I2S source clock selection EPLL reference clock
		else
			rCLKSRC = (rCLKSRC & ~(3<<14)) | (3<<14); // I2S source clock selection EPLL reference clock

		Delay(100);
				
		// IIS clock register setting
		rIISMOD = ( rIISMOD & ~(0x7<<10) ) | (0<<12)| (3<<10); //internal codec clock source, slave, pclki2sclk(dont care)
		rIISPSR = (0<<15)|(1<<8); //[15] 0 prescaler disable->bypass, /2 will not affected
	}
	else
	{
	// clock gating
		rPCLKCON = (rPCLKCON & ~(1<<17)) | (1<<17); // PCLK bus block of i2s enable
		rSCLKCON = (rSCLKCON& ~(1<<5)) | (1<<5); // I2S source clock enable

		printf("set i2s clock source 0. disalbe cdclk out, 2. EPLLref 3. EPLLref[D] \n");
		num = GetIntNum();
		if(  num == 0)
			rSCLKCON = (rSCLKCON& ~(1<<5)) | (1<<5); // I2S source clock disable, cdclk out will be blocked
		else if(  num == 2)
			rCLKSRC = (rCLKSRC & ~(3<<12)) | (2<<12); // I2S source clock selection EPLL reference clock	
		else
			rCLKSRC = (rCLKSRC & ~(3<<12)) | (3<<12); // I2S source clock selection EPLL reference clock

		Delay(100);

		rIISMOD1 = ( rIISMOD1 & ~(0x7<<10) ) | (0<<12) | (3<<10);//internal codec clock source, slave, pclki2sclk(dont care)
		rIISPSR1 = (0<<15)|(1<<8);//[15] 0 prescaler disable->bypass , /2 will not affected
	}

}


//=================================== [ IIS Test codes ] ==================================

void __irq DMA2_Done(void)
{
	rINTSUBMSK |= BIT_SUB_DMA2; 	
	rINTMSK |= (BIT_DMA);
	rSUBSRCPND = BIT_SUB_DMA2;
	ClearPending(BIT_DMA);	

/*	rIISCON	&= ~(1<<2)|(0<<0);


	//fifo control