pcm_test.c

samsung 最新芯片2450 的测试程序.

	printf("paused for test\n");

	printf("\n## PCM_TX_DMA_EN enable test##\n");
	tc1 = rDSTAT1 & 0xfffff;
	printf("tc1:%d\n", tc1);
	PCM_fifostat();	


	if(g_oPCMState.PCMPort==0) 	j = 32-TXFIFO_DIPSTICK0-1-FIFO_TXFIFO_COUNT0;//target : 32-txfifo_dipstick1-1
	else							j = 32-TXFIFO_DIPSTICK1-1-FIFO_TXFIFO_COUNT1;//target : 32-txfifo_dipstick1-1
	//write until almost full-1
	if(j<0) 
	{
		for(i=0 ; i>j; i--)
		{
			testreg=*rPCM_TXFIFO;
			PCM_fifostat();
			printf("^--one read\n");
		}		
	}
	else
	{
		for(i=0 ; i<j; i++)
		{
			*rPCM_TXFIFO = 0x1111;
			PCM_fifostat();
		}		
	}
	
	Delay(10);//1ms
	
	tc2 = rDSTAT1 & 0xfffff;	
	printf("==>tc2:%d\n", tc2);
	PCM_fifostat();
	if(tc2 != (tc1-2) ) failnum++;
	
	//test 2 : after disable
	*rPCM_CTL&= ~(PCM_TX_DMA_EN);
	printf("\n## PCM_TX_DMA_EN disable test ##\n");
	tc1 = rDSTAT1 & 0xfffff;
	printf("tc1:%d\n", tc1);
		
	testreg=*rPCM_TXFIFO;
	printf("one read\n");
	testreg=*rPCM_TXFIFO;
	printf("one read\n");

	Delay(10);//1ms
	tc2 = rDSTAT1 & 0xfffff;
	printf("==>tc2:%d\n", tc2);
	PCM_fifostat();	
	if(tc2 != tc1 ) failnum++;	
	
	if(failnum==0) return 1;
	else return 0;
}


//verify : pcm_pcm_enable : 0 =>shifter register counter held in reset ,sout toggle will not toggle.
//        fifo count will be same. (fifo data will not be trasmitted via shift engine to output)
//		affectness : when reset in the middle of data sending.
//specify how it work :       
//test scenario : in the middle of dma recording set PCM_TX_DMA_EN to 0

bool PCM_Detail_PCM_PCM_ENABLE_TX()
{
	int i=0;
	int ch;
	bool soutlow=FALSE;
	int failnum=0;
	int fifocnt1, fifocnt2;
	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;	
	
	PCM_SetInt(TXFIFO_ERROR_OVERFLOW);
	PCM_EnableInt();
	
	PCM_fifostat();

	*rPCM_CTL&= ~(PCM_PCM_ENABLE);	
	
	printf("see the sout, this should be low. Is output low?\n");
	ch=getchar();
	if(ch=='Y' || ch=='y') soutlow = TRUE;
	if(soutlow!=TRUE) failnum++;

	PCM_fifostat();
	if(g_oPCMState.PCMPort==0) 	fifocnt1 = FIFO_TXFIFO_COUNT0;
	else 						fifocnt1 = FIFO_TXFIFO_COUNT1;
	printf("fifocnt1 : %d\n", fifocnt1);

	Delay(10000);//1sec
	
	PCM_fifostat();	
	if(g_oPCMState.PCMPort==0) 	fifocnt2 = FIFO_TXFIFO_COUNT0;
	else 						fifocnt2 = FIFO_TXFIFO_COUNT1;
	printf("fifocnt2 : %d\n", fifocnt2);

	if(fifocnt1!=fifocnt2) failnum++;
		
	if(failnum==0) return 1;
	else return 0;	
}



//verify : pcm_fifo_enable : 0 -internal fifos will clear and reinitialize
//specify how it work :       when disabled fifo count should be cleared.
//test scenario : in the middle of dma recording set PCM_TX_DMA_EN to 0

bool PCM_Detail_PCM_FIFOENABLE_TX()
{
	int i, j;
	int fifocnt1, fifocnt2;
	int testreg;
	
	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;	
	
	PCM_DisableInt();	


	//stop middle of playing
	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//dma disalbe for fifo control

	PCM_fifostat();
	j=(g_oPCMState.PCMPort==0)?FIFO_TXFIFO_COUNT0 : FIFO_TXFIFO_COUNT1;
	//0. fifo will be emptied for purpose.
	printf("0. fifo will be emptied for purpose.\n");
	for(i=0;i<j;i++)
	{
		testreg = *rPCM_TXFIFO;
		PCM_fifostat();	
	}
	
	printf("0. fifo will be fulled for the purpose.\n");
	
	for(i=0;i<j+1;i++)
	{
		*rPCM_TXFIFO = 0xff00 + i;
		PCM_fifostat();	
	}
	
	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();
	
	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();


	printf("\n## now txfifo will be disabled ##\n");	
	*rPCM_CTL&= ~PCM_TXFIFO_EN;
	fifocnt1 =(g_oPCMState.PCMPort==0)?FIFO_TXFIFO_COUNT0 : FIFO_TXFIFO_COUNT1;
	printf("fifocnt1 : %d\n", fifocnt1);	
///	//1. data valid should be 'not valid'
//	printf("1. data valid should be not valid\n");
//	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
//	PCM_fifostat();	
	
	//2. writing data will be not possible.	
	printf("2. writing data will be not possible.	\n");
	printf("one write\n");
	*rPCM_TXFIFO = 0x1111;
	PCM_fifostat();	

	printf("one write\n");
	*rPCM_TXFIFO = 0x1111;
	PCM_fifostat();	
	
	printf("one write\n");	
	*rPCM_TXFIFO = 0x1111;
	PCM_fifostat();	

	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();		
	
	
	//3. if enabled again fifo will not be showed fifo data.
	printf("\n3. if enabled again fifo will not be showed fifo data.\n");
	*rPCM_CTL|= PCM_TXFIFO_EN;
	
	printf("one read\n");		
	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();		

	printf("one read\n");		
	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();		
	
	fifocnt2 = FIFO_TXFIFO_COUNT;
	printf("fifocnt2 : %d\n", fifocnt2);	
	PCM_fifostat();

	
	if( fifocnt1 ==0 && fifocnt2==0) return 1;
	else return 0;	
}




//verify : ctl_serclk_en : low
//specify how it work :    pcmsclk pcmfsync operate.
//test scenario : in the middle of dma recording set PCM_TX_DMA_EN to 0
bool PCM_Detail_CTL_SERCLK_EN_TX()
{
	int i=0;
	int fifocnt1, fifocnt2, fifocnt3;
	int	tc1, tc2, tc3;
	
	int ch;
	int j, testreg;
	bool serclklow=FALSE;
	int failnum=0;
	
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;	
	
	
	PCM_DisableInt();	

	//stop middle of playing
	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	tc1 = rDSTAT1 & 0xfffff;
	fifocnt1 = (g_oPCMState.PCMPort==0)?FIFO_TXFIFO_COUNT0 : FIFO_TXFIFO_COUNT1;
	
	printf("0. see fsync, sclk, is low?\n");
	ch=getchar();	
	if(ch=='Y' || ch=='y') serclklow = TRUE;
	
	//dma, fifo count should be same.
	tc2 = rDSTAT1 & 0xfffff;
	fifocnt2 = (g_oPCMState.PCMPort==0)?FIFO_TXFIFO_COUNT0 : FIFO_TXFIFO_COUNT1;


	if(tc1 != tc2)	failnum++;
	if(fifocnt1 != fifocnt2)	failnum++;
	if( !serclklow)	failnum++;


	//if fifo read will cause dma request, fifo will be filled.
	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();
	printf("txfifo : 0x%x\n", *rPCM_TXFIFO);	
	PCM_fifostat();	


	for(i=0; i<0xffff ;i++) ;
	
	
	tc3 = rDSTAT1 & 0xfffff;
	fifocnt3 = (g_oPCMState.PCMPort==0)?FIFO_TXFIFO_COUNT0 : FIFO_TXFIFO_COUNT1;

	if(tc3 != (tc2-2))	failnum++;
	if(fifocnt2 != fifocnt3)	failnum++;

	printf("fc1:%d,fc2:%d,fc3:%d\n", fifocnt1, fifocnt2, fifocnt3);
	printf("tc1:0x%x,tc2:0x%x,tc3:0x%x\n", tc1, tc2, tc3);
	
	
	if(failnum==0) return 1;
	else return 0;
}





//verify : interrupt pending - irq_pending 1, txfifo_almostfull (fifocnt>24)
//specify how it work :       ISR occur - g_interrupt_cnt should be incresed.
//							  writing any value to clrint, 
//							  pcm_irq_stat 's irq pending should be cleared.
//							  bit relating certain interupt should be cleared
bool PCM_Detail_PCM_IRQ_TXALMOSTFULL()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;

	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;
	
	
	PCM_DisableInt();
	
	PCM_fifostat();

	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//pause	+ dma disalbe for fifo control
	
	j = (g_oPCMState.PCMPort==0)? 32-TXFIFO_DIPSTICK0-FIFO_TXFIFO_COUNT0 :
			32-TXFIFO_DIPSTICK1-FIFO_TXFIFO_COUNT1;//target -  32-txfifo_dipstick
	
	//write until almost full
	if(j<0) 
	{
		for(i=0 ; i>j; i--)
		{
			testreg=*rPCM_TXFIFO;
			PCM_fifostat();
			printf("^--one read\n");
		}		
	}
	else
	{
		for(i=0 ; i<j; i++)
		{
			*rPCM_TXFIFO = 0x1111;
			PCM_fifostat();
			printf("^--one write\n");
		}		
	}
	//now 24
	PCM_SetInt(TXFIFO_ALMOST_FULL);	
	PCM_EnableInt();	

	irqcnt1 = g_interrupt_cnt;
	
	//to make almost full (25)
	*rPCM_TXFIFO = 0x1111;
	PCM_fifostat();
	
	//wait for IRQ for secure
	i=0;
	while( g_interrupt_cnt ==0 )
	{
		i++;
		if(i>0xffff) break;
	}		
	irqcnt2 = g_interrupt_cnt;
	
	if(irqcnt2 == (irqcnt1 +1 ) ) 
	{
		int pendingcnt=0;
		//ok. interrupt is occured.
		
		if( g_pcmirqstat[irqcnt1].irqstat1 & IRQ_PENDING ) 
		{
			printf("irq pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_ALMOST_FULL ) 
		{
			printf("tx almost full pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );	
			pendingcnt++;
		}
		
		if( g_pcmirqstat[irqcnt1].irqstat2 & IRQ_PENDING )
		{
			printf("irq pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat2 & TXFIFO_ALMOST_FULL ) 
		{
			printf("tx almost full pending2 0x%x\n",g_pcmirqstat[irqcnt2].irqstat2 );	
			pendingcnt++;
		}
		
		printf("irq stat1 0x%x\n",g_pcmirqstat[irqcnt1].irqstat1 );
		printf("irq stat2 0x%x\n",g_pcmirqstat[irqcnt1].irqstat2 );
		
		if( pendingcnt ==2 )
		{
			printf("ok\n");	
			return TRUE;
		}
		
	}
		
	//printf("rx fifo 0x%x \n",rPCM_RXFIFO1);
	//PCM_fifostat();	
		
	return FALSE;
}



//verify : interrupt pending - irq_pending 1, txfifo_full
//specify how it work :       ISR occur - g_interrupt_cnt should be incresed.
//							  writing any value to clrint, 
//							  pcm_irq_stat 's irq pending should be cleared.
//							  bit relating certain interupt should be cleared
bool PCM_Detail_PCM_IRQ_TXFULL()
{
	int i=0;
	int irqcnt1, irqcnt2;
	int j, testreg;

	unsigned int *rPCM_CTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CTL0:(unsigned int *)&rPCM_CTL1;
	unsigned int *rPCM_CLKCTL=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_CLKCTL0:(unsigned int *)&rPCM_CLKCTL1;
	unsigned int *rPCM_TXFIFO=(g_oPCMState.PCMPort==0)?(unsigned int *)&rPCM_TXFIFO0:(unsigned int *)&rPCM_TXFIFO1;
	
	
	PCM_SetInt(TXFIFO_FULL);	
	PCM_EnableInt();	
	
	PCM_fifostat();

	*rPCM_CLKCTL&= ~(PCM_SCLK_EN);		
	*rPCM_CTL&= ~(PCM_PCM_ENABLE|PCM_TX_DMA_EN);//pause	+ dma disalbe for fifo control

	PCM_fifostat();	
	j = (g_oPCMState.PCMPort==0)? 32-FIFO_TXFIFO_COUNT0-1:
			32-FIFO_TXFIFO_COUNT1-1;//target -  32-1

	//write until full -1
	if(j<0) 
	{
		for(i=0 ; i>j; i--)
		{
			testreg=*rPCM_TXFIFO;
			PCM_fifostat();
			printf("^--one read\n");			
		}		
	}
	else
	{
		for(i=0 ; i<j; i++)
		{
			*rPCM_TXFIFO = 0x1111;
			PCM_fifostat();
			printf("^--one write\n");			
		}		
	}

	irqcnt1 = g_interrupt_cnt;
	
	//to make full
	*rPCM_TXFIFO = 0x1111;
	PCM_fifostat();	
	
	//wait for IRQ for secure
	i=0;
	while( g_interrupt_cnt ==0 )
	{
		i++;
		if(i>0xffff) break;
	}		
	irqcnt2 = g_interrupt_cnt;
	
	if(irqcnt2 == (irqcnt1 +1 ) ) 
	{
		int pendingcnt=0;
		//ok. interrupt is occured.
		
		if( g_pcmirqstat[irqcnt1].irqstat1 & IRQ_PENDING ) 
		{
			printf("irq pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );
			pendingcnt++;
		}
		if( g_pcmirqstat[irqcnt1].irqstat1 & TXFIFO_FULL ) 
		{
			printf("tx full pending1 0x%x\n",g_pcmirqstat[irqcnt2].irqstat1 );	
			pendingcnt++;
		}