adder.vhd

来自「几个稍微深入的时序逻辑电路和状态机的VHDL代码」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder is port (
  a,b: in unsigned(3 downto 0);
  sum: out unsigned(3 downto 0)
  );
end adder;

architecture simple of adder is

begin

  sum <= a + b;

end simple;