📄 csc_top_map.mrp

📁 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.
💻 MRP
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Release 4.2.03i - Map E.38Xilinx Mapping Report File for Design 'csc_top'Design Information------------------Command Line   : map -pr b -detail csc_top.ngd -o csc_top_map.ncd csc_top.pcf Target Device  : x2vp2Target Package : fg256Target Speed   : -6Mapper Version : virtex2p -- $Revision: 1.58 $Mapped Date    : Fri Aug 02 15:14:46 2002Design Summary--------------   Number of errors:      0   Number of warnings:    0   Number of Slices:                  178 out of   1,408   12%   Number of Slices containing      unrelated logic:                  0 out of     178    0%   Number of Slice Flip Flops:        258 out of   2,816    9%   Total Number 4 input LUTs:         258 out of   2,816    9%      Number used as LUTs:                          218      Number used as a route-thru:                   40   Number of bonded IOBs:              63 out of     140   45%      IOB Flip Flops:                                60   Number of GCLKs:                     1 out of      16    6%Total equivalent gate count for design:  5,361Additional JTAG gate count for IOBs:  3,024Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:354 - Virtex BUFGP symbol "Clock_ibuf" (output signal=Clock_c) is
   being retargetted to Virtex2 BUFGMUX with input tied to I0 and Select pin
   tied to constant 0.INFO:MapLib:159 - Net Timing constraints on signal Clock are pushed forward
   through input buffer.INFO:MapLib:62 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary---------------------------------  36 block(s) optimized away 316 Block(s) redundantSection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		CSC_module/Cb_KCM_blue/GNDVCC 		CSC_module/Cb_KCM_blue/VCCLUT1 		CSC_module/Cb_KCM_blue/un1_un1_color_0_axb_13GND 		CSC_module/Cb_KCM_green/GNDGND 		CSC_module/Cb_KCM_red/GNDFDCE 		CSC_module/Cr_KCM_blue/Color_Out[0]GND 		CSC_module/Cr_KCM_blue/GNDLUT1 		CSC_module/Cr_KCM_blue/un1_un1_color_axb_14GND 		CSC_module/Cr_KCM_green/GNDVCC 		CSC_module/Cr_KCM_green/VCCLUT1 		CSC_module/Cr_KCM_green/un1_un1_color_0_axb_14LUT1 		CSC_module/Cr_KCM_green/un1_un1_color_1_axb_11GND 		CSC_module/Cr_KCM_red/GNDVCC 		CSC_module/Cr_KCM_red/VCCLUT1 		CSC_module/Cr_KCM_red/un1_un1_color_0_axb_13GND 		CSC_module/GNDVCC 		CSC_module/VCCGND 		CSC_module/Y601_KCM_blue/GNDGND 		CSC_module/Y601_KCM_green/GNDLUT1 		CSC_module/Y601_KCM_green/un1_un1_color_axb_17GND 		CSC_module/Y601_KCM_red/GNDLUT1 		CSC_module/Y601_KCM_red/un1_un1_color_axb_16FDCE 		CSC_module/cb_cst_b[3]FDCE 		CSC_module/cb_red_green[0]FDCE 		CSC_module/cr_green_blue[0]LUT2 		CSC_module/un7_cb_red_green_axb_0LUT2 		CSC_module/un7_cb_red_green_axb_17LUT2 		CSC_module/un7_cr_green_blue_axb_0LUT2 		CSC_module/un7_y_red_blue_axb_17LUT2 		CSC_module/un8_cb_full_axb_0LUT2 		CSC_module/un8_cr_full_axb_0MUXCY_L 		CSC_module/un7_cb_red_green_cry_0MUXCY_L 		CSC_module/un7_cr_green_blue_cry_0MUXCY_L 		CSC_module/un7_y_red_blue_cry_0MUXCY_L 		CSC_module/un8_cb_full_cry_0MUXCY_L 		CSC_module/un8_cr_full_cry_0Redundant Block(s):TYPE 		BLOCKLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_15/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_14/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_13/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_12/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_11/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_10/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_9/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_red/un1_un1_color_cry_6/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_16/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_15/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_14/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_13/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_12/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_11/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_10/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_9/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_green/un1_un1_color_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_6/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_5/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_4/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_3/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_2/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_1/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_1_cry_0/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_6/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_5/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_4/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_3/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_2/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_1/MUXCY_L_BUFLOCALBUF 		CSC_module/Y601_KCM_blue/un1_un1_color_0_cry_0/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_6/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_5/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_4/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_3/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_2/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_1/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_1_cry_0/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_6/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_5/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_4/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_3/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_2/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_1/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_red/un1_un1_color_0_cry_0/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_8/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_7/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_6/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_5/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_4/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_3/MUXCY_L_BUFLOCALBUF 		CSC_module/Cb_KCM_green/un1_un1_color_1_cry_2/MUXCY_L_BUF
12 3 下一页
💿 文件大小 403 K
👤 上传用户 fscdif
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#verilog #xilinx #FPGA #CbCr
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