mctrl.vhd

来自「宇航级微处理器LEON2 2.2 VHDL源代码,很难找的.」· VHDL 代码 · 共 690 行 · 第 1/2 页

      else
        writedata(31 downto 24) :=  r.data(31 downto 24);
      end if;
    end if;



-- save read data during 8/16 bit reads

    if BUS8EN and (b8reg.ready = '1') and (r.busw = "00") then
      v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
    elsif BUS16EN and (b8reg.ready = '1') and (r.busw = "01") then
      v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
    end if;

-- Ram, rom, IO access FSM

    if r.read = '1' then wsnew := rws; else wsnew := wws; end if;

    case r.bstate is
    when idle =>
      v.ws := wsnew; 
      if r.bdrive(0) = '0' then v.writedata := writedata; end if;
      if r.hsel = '1' then
	wprothitx := wpo.wprothit and not r.read;
	if (wprothitx or addrerr) = '1' then
	  v.hresp := HRESP_ERROR; v.bstate := berr;
	elsif r.read = '0' then 
	  if (r.busw = "00") and BUS8EN then v.bstate := bwrite8;
	  elsif (r.busw = "01") and BUS16EN then v.bstate := bwrite16;
   	  else v.bstate := bwrite; end if;
	  v.wrn := wrn; v.writen := '0'; v.bdrive := bdrive;
	else 
	  if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
	  else
	    if (r.busw = "00") and BUS8EN then v.bstate := bread8;
	    elsif (r.busw = "01") and BUS16EN then v.bstate := bread16;
	    else v.bstate := bread; end if;
	  end if;
	end if;
      end if;
    when berr =>
      v.bstate := idle; v.hsel := '0'; ready := '1';
      v.hresp := HRESP_ERROR;
      v.ramsn := (others => '1'); v.romsn := (others => '1');
      v.ramoen := (others => '1'); v.oen := '1'; v.iosn := '1';
    when bread => 
      if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
      then 
	if r.brmw = '0' then
	  ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
	end if;
        if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or (r.hburst = HBURST_SINGLE))
        then
	  if r.brmw = '0' then
  	    v.ramsn := (others => '1'); v.romsn := (others => '1'); v.hsel := '0';
	  end if;
  	  v.ramoen := (others => '1'); v.oen := '1'; v.iosn := '1';
   	  v.bstate := idle; v.read := not r.hwrite;
	end if;
      end if;
      if r.ready = '1' then
	v.ws := rws;
      else
	if r.ws /= "0000" then v.ws := r.ws - 1; end if;
      end if;
    when bwrite =>
      if (r.ws = "0000") and (bready = '1') then
	ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
	v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := '1';
	v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
      end if;
      if r.ws /= "0000" then v.ws := r.ws - 1; end if;
    when bread8 => 
      if BUS8EN then
        if (r.ws = "0000") and (r.address(1 downto 0) = "11") and 
	   (b8reg.ready = '0') 
        then
	  ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
          if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or 
	      (r.hburst = HBURST_SINGLE))
          then
  	    v.ramsn := (others => '1'); v.romsn := (others => '1');
  	    v.ramoen := (others => '1'); v.oen := '1'; v.iosn := '1';
   	    v.bstate := idle; v.hsel := '0';
	  end if;
        end if;
        if (r.ws = "0000") and (b8reg.ready = '0') then 
	  b8v.ready := '1'; v.ws := rws; 
	  v.address(1 downto 0) := r.address(1 downto 0) + 1;
        end if;
        if r.ws /= "0000" then v.ws := r.ws - 1; end if;
      end if;
    when bwrite8 =>
      if BUS8EN then
        if (r.ws = "0000") and 
           ((r.address(1 downto 0) = "11") or 
            ((r.address(1 downto 0) = "01") and (r.size = "01")) or
	    (r.size = "00")) 
        then
	  ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
	  v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := '1';
	  v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
        end if;
        if (r.ws = "0000") and (b8reg.ready = '0') then 
	  b8v.ready := '1'; v.wrn := (others => '1'); v.writen := '1';
        end if;
        if (b8reg.ready = '1') then
	  v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws; 
	  v.writedata(31 downto 8) := r.writedata(23 downto 0);
	  v.bstate := idle; 
        end if;
        if r.ws /= "0000" then v.ws := r.ws - 1; end if;
      end if;
    when bread16 => 
      if BUS16EN then
        if (r.ws = "0000") and ((r.address(1) or r.brmw) = '1') and 
	   (b8reg.ready = '0') 
        then
	  if r.brmw = '0' then
	    ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
	  end if;
          if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or 
	      (r.hburst = HBURST_SINGLE))
          then
	    if r.brmw = '0' then
  	      v.ramsn := (others => '1'); v.romsn := (others => '1'); v.hsel := '0';
	    end if;
  	    v.ramoen := (others => '1'); v.oen := '1'; v.iosn := '1';
   	    v.bstate := idle; v.read := not r.hwrite;
	  end if;
        end if;
        if (r.ws = "0000") and (b8reg.ready = '0') then 
	  b8v.ready := '1'; v.ws := rws; 
	  if r.brmw = '0' then v.address(1) := not r.address(1); end if;
        end if;
        if r.ws /= "0000" then v.ws := r.ws - 1; end if;
      end if;
    when bwrite16 =>
      if BUS16EN then
        if (r.ws = "0000") and 
           ((r.address(1 downto 0) = "10") or (r.size(1) = '0')) 
        then
	  ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
	  v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := '1';
	  v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
        end if;
        if (r.ws = "0000") and (b8reg.ready = '0') then 
	  b8v.ready := '1'; v.wrn := (others => '1'); v.writen := '1';
        end if;
        if (b8reg.ready = '1') then
	  v.address(1) := not r.address(1); v.ws := rws; 
	  v.writedata(31 downto 16) := r.writedata(15 downto 0);
	  v.bstate := idle; 
        end if;
        if r.ws /= "0000" then v.ws := r.ws - 1; end if;
      end if;
    when others =>
    end case;

-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
    if (ahbsi.hready = '1') then
      if ((ahbsi.hsel = '0') or (ahbsi.htrans = HTRANS_BUSY) or 
	(ahbsi.htrans = HTRANS_IDLE))
      then
        v.bstate := idle;
        v.ramsn := (others => '1'); v.romsn := (others => '1');
        v.ramoen := (others => '1'); v.oen := '1'; v.iosn := '1';
        v.bdrive := (others => '0'); v.wrn := (others => '1');
        v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel;
      elsif ahbsi.hsel = '1' then
        v.romsn := romsn; v.ramsn := ramsn; v.iosn := iosn; v.hsel := '1';
        if v.read = '1' then v.ramoen := ramsn; v.oen := leadin; end if;
      end if;
    end if;

-- error checking and reporting

    noerror := '1';
    if ((r.echeck and not r.bexcn) = '1') then
      noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR;
    end if;
     
-- APB register access

    case apbi.paddr(3 downto 2) is
    when "00" => 
      regsd(28 downto 0) := r.mcfg1.iowidth & 
	r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
	r.mcfg1.extlatch & 

	"000000" & r.mcfg1.romwrite & 

	'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
    when "01" => 
      regsd(12 downto 0) := r.mcfg2.rambanksz & "00" & r.mcfg2.rmw &
	r.mcfg2.ramwidth & r.mcfg2.ramwws & r.mcfg2.ramrws;

    when others => regsd := (others => '0');
    end case;

    apbo.prdata <= regsd;

    if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
      case apbi.paddr(5 downto 2) is
      when "0000" => 
        v.mcfg1.romrws      :=  apbi.pwdata(3 downto 0); 
        v.mcfg1.romwws      :=  apbi.pwdata(7 downto 4);
        v.mcfg1.romwidth    :=  apbi.pwdata(9 downto 8);
        v.mcfg1.romwrite    :=  apbi.pwdata(11);

        v.mcfg1.extlatch    :=  apbi.pwdata(18);
        v.mcfg1.ioen        :=  apbi.pwdata(19);
        v.mcfg1.iows        :=  apbi.pwdata(23 downto 20);
        v.mcfg1.bexcen      :=  apbi.pwdata(25);
        v.mcfg1.brdyen      :=  apbi.pwdata(26);
        v.mcfg1.iowidth     :=  apbi.pwdata(28 downto 27);
      when "0001" => 
        v.mcfg2.ramrws      := apbi.pwdata(1 downto 0);
        v.mcfg2.ramwws      := apbi.pwdata(3 downto 2);
        v.mcfg2.ramwidth    := apbi.pwdata(5 downto 4);
        v.mcfg2.rmw         := apbi.pwdata(6);
        v.mcfg2.rambanksz   := apbi.pwdata(12 downto 9);

      when others => null;
      end case;
    end if;

-- select appropriate data during reads


    case r.area is
    when rom | ram => 

	if (BOOTOPT = prom) and (r.area = rom) then 
	  v.readdata := promdata; dataout := r.readdata;
        else dataout := memdata; end if;

    when io => dataout := r.data;
    end case;





    v.ready := ready;

-- generate memory address

    if RAWADDR and (r.mcfg1.extlatch = '1') then
      memo.address <= v.address(27 downto 0);
    else
      memo.address <= r.address(27 downto 0);
    end if;

-- use d(15:0) as input ports (only usefull in 8-bit mode)

    if BUS8EN or BUS16EN then mctrlo.pioh <= r.data(15 downto 0);
    else mctrlo.pioh <= (others => '0'); end if;

-- reset

    if rst.syncrst = '0' then

      v.bstate 	 	   := idle; 
      v.read 		   := '1'; 
      v.pwd 		   := '0';
      v.wrn                := "1111";
      v.writen		   := '1'; 
      v.mcfg1.romwrite     := '0';
      v.mcfg1.extlatch     := '0';
      v.mcfg1.ioen         := '0';
      v.mcfg1.brdyen       := '0';
      v.mcfg1.bexcen       := '0';
      v.hsel		   := '0';
      if BOOTOPT /= memory then
	v.mcfg2.ramrws	   := std_logic_vector(BRAMRWS(1 downto 0));
	v.mcfg2.ramwws	   := std_logic_vector(BRAMWWS(1 downto 0));
        v.mcfg1.romrws     := "0001";
        v.mcfg1.romwws     := "0001";
        v.mcfg1.romwidth   := "11";
      else
        v.mcfg1.romrws     := "1111";
        v.mcfg1.romwws     := "1111";
        v.mcfg1.romwidth   := pioo.io8lsb(1 downto 0);
      end if;
    end if;

-- pragma translate_off
    if is_x(dataout) then dataout := (others => '1'); end if;
-- pragma translate_on

-- drive various register inputs and external outputs

    ri <= v; b8regin <= b8v;


    memo.ramsn    	<= r.ramsn;
    memo.ramoen     	<= r.ramoen;
    if BOOTOPT /= prom then memo.romsn(0) <= r.romsn(0);
    else memo.romsn(0) <= '1'; end if;
    memo.romsn(1)    	<= r.romsn(1);
    memo.oen  		<= r.oen;
    memo.iosn  		<= r.iosn;
    memo.read  		<= r.read;
    memo.wrn 		<= r.wrn; 
    memo.writen 	<= r.writen;
    memo.bdrive  	<= (not r.bdrive) and memi.wrn;
    memo.data		<= r.writedata;


    ahbso.hrdata <= dataout;
    ahbso.hready <= r.ready and noerror;
    ahbso.hresp  <= r.hresp;
    ahbso.hsplit <= (others => '0');

  end process;


  stdregs : process(clk,rst)
  begin 
    if rising_edge(clk) then r <= ri; end if;
    if rst.rawrst = '0' then
      r.ramsn <= (others => '1'); r.romsn <= (others => '1');
      r.oen <= '1'; r.bdrive <= (others => '0');
      r.iosn <= '1'; r.ramoen <= (others => '1');
    end if;
  end process;

  b8reggen : if BUS8EN or BUS16EN generate 
    b8regs : process(clk)
    begin if rising_edge(clk) then b8reg <= b8regin; end if; end process;
  end generate;



-- optional boot-prom
 promgen : if (BOOTOPT = prom) generate
    bprom0 : bprom port map
      (clk => clk, cs => r.romsn(0), addr => r.address, data => promdata);
  end generate;

end;