tech_virtex.vhd

宇航级微处理器LEON2 2.2 VHDL源代码,很难找的.

----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.


-----------------------------------------------------------------------------
-- Package: 	tech_virtex
-- File:	tech_virtex.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Xilinx Virtex specific regfile and cache ram generators
------------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.std_logic_1164.all;

package tech_virtex is

component virtex_syncram
  generic ( abits : integer := 10; dbits : integer := 8 );
  port (
    address  : in std_logic_vector((abits -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((dbits -1) downto 0);
    dataout  : out std_logic_vector((dbits -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end component;

-- three-port regfile with sync read, sync write
  component virtex_regfile_ss
  generic ( 
    abits : integer := 8; dbits : integer := 32; words : integer := 128
  );
  port (
    clk      : in std_logic;
    datain   : in std_logic_vector (dbits -1 downto 0);
    raddr1   : in std_logic_vector (abits -1 downto 0);
    raddr2   : in std_logic_vector (abits -1 downto 0);
    waddr    : in std_logic_vector (abits -1 downto 0);
    enable   : in std_logic;
    write    : in std_logic;
    dataout1 : out std_logic_vector (dbits -1 downto 0);
    dataout2 : out std_logic_vector (dbits -1 downto 0));
  end component;

component virtex_boot_cache_mem
  generic ( 
    itdbits : integer := 10; itabits : integer := 8;
    iddbits : integer := 10; idabits : integer := 8;
    dtdbits : integer := 10; dtabits : integer := 8;
    dddbits : integer := 10; ddabits : integer := 8
  );
  port (
    clk       : in std_logic;
    enable    : in std_logic;
    itaddr    : in std_logic_vector((itabits -1) downto 0);
    itdatain  : in std_logic_vector((itdbits -1) downto 0);
    itdataout : out std_logic_vector((itdbits -1) downto 0);
    itwrite   : in std_logic;
    idaddr    : in std_logic_vector((idabits -1) downto 0);
    iddatain  : in std_logic_vector((iddbits -1) downto 0);
    iddataout : out std_logic_vector((iddbits -1) downto 0);
    idwrite   : in std_logic;
    dtaddr    : in std_logic_vector((dtabits -1) downto 0);
    dtdatain  : in std_logic_vector((dtdbits -1) downto 0);
    dtdataout : out std_logic_vector((dtdbits -1) downto 0);
    dtwrite   : in std_logic;
    ddaddr    : in std_logic_vector((ddabits -1) downto 0);
    dddatain  : in std_logic_vector((dddbits -1) downto 0);
    dddataout : out std_logic_vector((dddbits -1) downto 0);
    ddwrite   : in std_logic
  );
end component;

component virtex_bprom
  port (
    clk       : in std_logic;
    addr      : in std_logic_vector(29 downto 0);
    data      : out std_logic_vector(31 downto 0)
  );
end component;

end;

-- xilinx pre-loaded cache

-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;

entity tag128v4 is port (
  addr: in  std_logic_vector(6 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity tag128v8 is port (
  addr: in  std_logic_vector(6 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity tag256v4 is port (
  addr: in  std_logic_vector(7 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity tag256v8 is port (
  addr: in  std_logic_vector(7 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity tag512v4 is port (
  addr: in  std_logic_vector(8 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(23 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(23 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity data256 is port (
  addr: in  std_logic_vector(7 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity data512 is port (
  addr: in  std_logic_vector(8 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity data1024 is port (
  addr: in  std_logic_vector(9 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

library IEEE;
use IEEE.std_logic_1164.all;

entity data2048 is port (
  addr: in  std_logic_vector(10 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end ;

-- pragma translate_on
library IEEE;
use IEEE.std_logic_1164.all;

entity virtex_boot_cache_mem is
  generic ( 
    itdbits : integer := 10; itabits : integer := 8;
    iddbits : integer := 10; idabits : integer := 8;
    dtdbits : integer := 10; dtabits : integer := 8;
    dddbits : integer := 10; ddabits : integer := 8
  );
  port (
    clk       : in std_logic;
    enable    : in std_logic;
    itaddr    : in std_logic_vector((itabits -1) downto 0);
    itdatain  : in std_logic_vector((itdbits -1) downto 0);
    itdataout : out std_logic_vector((itdbits -1) downto 0);
    itwrite   : in std_logic;
    idaddr    : in std_logic_vector((idabits -1) downto 0);
    iddatain  : in std_logic_vector((iddbits -1) downto 0);
    iddataout : out std_logic_vector((iddbits -1) downto 0);
    idwrite   : in std_logic;
    dtaddr    : in std_logic_vector((dtabits -1) downto 0);
    dtdatain  : in std_logic_vector((dtdbits -1) downto 0);
    dtdataout : out std_logic_vector((dtdbits -1) downto 0);
    dtwrite   : in std_logic;
    ddaddr    : in std_logic_vector((ddabits -1) downto 0);
    dddatain  : in std_logic_vector((dddbits -1) downto 0);
    dddataout : out std_logic_vector((dddbits -1) downto 0);
    ddwrite   : in std_logic
  );
end;

architecture rtl of virtex_boot_cache_mem is
component tag128v4 port (
  addr: in  std_logic_vector(6 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component tag128v8 port (
  addr: in  std_logic_vector(6 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component tag256v4 port (
  addr: in  std_logic_vector(7 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component tag256v8 port (
  addr: in  std_logic_vector(7 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component tag512v4 port (
  addr: in  std_logic_vector(8 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(23 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(23 downto 0));
end component;
component data256 port (
  addr: in  std_logic_vector(7 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component data512 port (
  addr: in  std_logic_vector(8 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component data1024 port (
  addr: in  std_logic_vector(9 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;
component data2048 port (
  addr: in  std_logic_vector(10 downto 0);
  clk : in  std_logic;
  di  : in  std_logic_vector(31 downto 0);
  we  : in  std_logic;
  en  : in  std_logic;
  rst : in  std_logic;
  do  : out std_logic_vector(31 downto 0));
end component;

signal itd, dtd, itdo, dtdo : std_logic_vector(32 downto 0);
signal ita, dta : std_logic_vector(12 downto 0);
signal idd, ddd, iddo, dddo : std_logic_vector(32 downto 0);
signal ida, dda : std_logic_vector(14 downto 0);
signal gnd : std_logic;
begin

  gnd <= '0';
  ita(itabits-1 downto 0) <= itaddr;
  ita(12 downto itabits) <= (others => '0');
  dta(dtabits-1 downto 0) <= dtaddr;
  dta(12 downto dtabits) <= (others => '0');
  itd(itdbits-1 downto 0) <= itdatain; 
  itd(32 downto itdbits) <= (others => '0');
  dtd(dtdbits-1 downto 0) <= dtdatain; 
  dtd(32 downto dtdbits) <= (others => '0');

  ida(idabits-1 downto 0) <= idaddr;
  ida(14 downto idabits) <= (others => '0');
  dda(ddabits-1 downto 0) <= ddaddr;
  dda(14 downto ddabits) <= (others => '0');
  idd(iddbits-1 downto 0) <= iddatain; 
  idd(32 downto iddbits) <= (others => '0');
  ddd(dddbits-1 downto 0) <= dddatain; 
  ddd(32 downto dddbits) <= (others => '0');

-- instruction tags

  itv4 : if itdbits <= 25 generate
    it128 : if itabits = 7 generate
      it0 : tag128v4 port map ( 
	addr => ita(6 downto 0), clk => clk, 
        di => itd(31 downto 0), en => enable, rst => gnd,
	we => itwrite, do => itdo(31 downto 0));
    end generate;
    it256 : if itabits = 8 generate
      it0 : tag256v4 port map ( 
	addr => ita(7 downto 0), clk => clk, 
        di => itd(31 downto 0), en => enable, rst => gnd,
	we => itwrite, do => itdo(31 downto 0));
    end generate;
    it512 : if itabits = 9 generate
      it0 : tag512v4 port map ( 
	addr => ita(8 downto 0), clk => clk, 
        di => itd(23 downto 0), en => enable, rst => gnd,
	we => itwrite, do => itdo(23 downto 0));
    end generate;
  end generate;

  itv8 : if itdbits > 25 generate
    it128 : if itabits = 7 generate
      it0 : tag128v8 port map ( 
	addr => ita(6 downto 0), clk => clk, 
        di => itd(31 downto 0), en => enable, rst => gnd,
	we => itwrite, do => itdo(31 downto 0));
    end generate;
    it256 : if itabits = 8 generate
      it0 : tag256v8 port map ( 
	addr => ita(7 downto 0), clk => clk, 
        di => itd(31 downto 0), en => enable, rst => gnd,
	we => itwrite, do => itdo(31 downto 0));
    end generate;
  end generate;

-- data tags

  dtv4 : if dtdbits <= 25 generate
    dt128 : if dtabits < 8 generate
      dt0 : tag128v4 port map ( 
	addr => dta(6 downto 0), clk => clk, 
        di => dtd(31 downto 0), en => enable, rst => gnd,
	we => dtwrite, do => dtdo(31 downto 0));
    end generate;
    dt256 : if dtabits = 8 generate
      dt0 : tag256v4 port map ( 
	addr => dta(7 downto 0), clk => clk, 
        di => dtd(31 downto 0), en => enable, rst => gnd,
	we => dtwrite, do => dtdo(31 downto 0));
    end generate;
    dt512 : if dtabits = 9 generate
      dt0 : tag512v4 port map ( 
	addr => dta(8 downto 0), clk => clk, 
        di => dtd(23 downto 0), en => enable, rst => gnd,
	we => dtwrite, do => dtdo(23 downto 0));
    end generate;
  end generate;

  dtv8 : if dtdbits > 25 generate
    dt128 : if dtabits < 8 generate
      dt0 : tag128v8 port map ( 
	addr => dta(6 downto 0), clk => clk, 
        di => dtd(31 downto 0), en => enable, rst => gnd,
	we => dtwrite, do => dtdo(31 downto 0));
    end generate;
    dt256 : if dtabits = 8 generate
      dt0 : tag256v8 port map ( 
	addr => dta(7 downto 0), clk => clk, 
        di => dtd(31 downto 0), en => enable, rst => gnd,
	we => dtwrite, do => dtdo(31 downto 0));
    end generate;
  end generate;

-- instruction data

  id1024 : if idabits < 9 generate
    id0 : data256 port map ( 
	addr => ida(7 downto 0), clk => clk, 
        di => idd(31 downto 0), en => enable, rst => gnd,
	we => idwrite, do => iddo(31 downto 0));