vga_card.vhd

VGA模块的VHDL代码和软件驱动

library IEEE;
use IEEE.std_logic_1164.all;

entity vga_card is
	port
	(
		clk:			in std_logic;	-- from bus
		clk_vga:		in std_logic;	-- for vga
		reset:			in std_logic;	-- from bus
		chipselect:		in std_logic;	-- from bus
		address:		in std_logic_vector( 17 downto 0 ); -- from bus
		read_n:			in std_logic;	-- from bus
		write_n:		in std_logic;	-- from bus
		writedata:		in std_logic_vector( 15 downto 0 ); -- from bus
		byteenable_n:	in std_logic_vector( 1 downto 0 ); -- from bus
		sram_dq:		inout std_logic_vector( 15 downto 0 );
		waitrequest:	out std_logic;	-- to bus
		readdata:		out std_logic_vector( 15 downto 0 ); -- to bus
		sram_addr:		out std_logic_vector( 17 downto 0 ); -- export to sram
		sram_we_n:		out std_logic;	-- export to sram
		sram_oe_n:		out std_logic;	-- export to sram
		sram_ub_n:		out std_logic;	-- export to sram
		sram_lb_n:		out std_logic;	-- export to sram
		sram_ce_n:		out std_logic;	-- export to sram
		vga_sync:		out std_logic;	-- export to vga
		vga_hsync:		out std_logic;	-- export to vga
		vga_vsync:		out std_logic;	-- export to vga
		vga_blank:		out std_logic;	-- export to vga
		vga_r:			out std_logic_vector( 9 downto 0 ); -- export to vga
		vga_g:			out std_logic_vector( 9 downto 0 ); -- export to vga
		vga_b:			out std_logic_vector( 9 downto 0 ) -- export to vga
	);
end vga_card;

architecture RTL of vga_card is
	
	component vga_display
		port
		(
			clk:		in std_logic; -- 25.2MHz
			ena:		in std_logic; -- from vga_ctrl
			data:		in std_logic_vector( 15 downto 0 ); -- from vga_ctrl
			addr:		out std_logic_vector( 16 downto 0 ); -- to vga_ctrl
			read_n:		out std_logic;	-- to vga_ctrl
			be_n:		out std_logic_vector( 1 downto 0 ); -- to vga_ctrl
			inuse:		out std_logic;	-- to vga_ctrl
			scan:		out std_logic;	-- to vga_ctrl
			vga_sync:	out std_logic;	-- to vga
			vga_hsync:	out std_logic;	-- to vga
			vga_vsync:	out std_logic;	-- to vga
			vga_blank:	out std_logic;	-- to vga
			vga_r:		out std_logic_vector( 9 downto 0 ); -- to vga
			vga_g:		out std_logic_vector( 9 downto 0 ); -- to vga
	--------------- for debug ---------------------
	--		ohodd:		out std_logic;
	--		ovodd:		out std_logic;
	--		ohscan:		out std_logic;
	--		ovscan:		out std_logic;
	--		ohcnt:		out integer range 0 to 799;
	--		ovcnt:		out integer range 0 to 525;
	-----------------------------------------------
			vga_b:		out std_logic_vector( 9 downto 0 ) -- to vga
		);
	end component;
	
	component vga_ctrl
		port
		(
			clk:			in std_logic;	-- from bus
			reset:			in std_logic;	-- from bus
			chipselect:		in std_logic;	-- from bus	
			address:		in std_logic_vector( 17 downto 0 ); -- from bus
			read_n:			in std_logic;	-- from bus
			write_n:		in std_logic;	-- from bus
			writedata:		in std_logic_vector( 15 downto 0 ); -- from bus
			byteenable_n:	in std_logic_vector( 1 downto 0 ); -- from bus
			vd_inuse:		in std_logic;	-- from vga_display (async)
			vd_scan:		in std_logic;	-- from vga_ctrl (async)
			vd_addr:		in std_logic_vector( 16 downto 0 ); -- from vga_display
			vd_read_n:		in std_logic;	-- from vga_display
			vd_be_n:		in std_logic_vector( 1 downto 0 ); -- from vga_display
			sram_dq:		inout std_logic_vector( 15 downto 0 );
			sram_addr:		out std_logic_vector( 17 downto 0 ); -- export to sram
			sram_we_n:		out std_logic;	-- export to sram
			sram_oe_n:		out std_logic;	-- export to sram
			sram_ub_n:		out std_logic;	-- export to sram
			sram_lb_n:		out std_logic;	-- export to sram
			sram_ce_n:		out std_logic;	-- export to sram
			vd_ena:			out std_logic;	-- to vga_display
			vd_data:		out std_logic_vector( 15 downto 0 ); -- to vga_display
			waitrequest:	out std_logic;	-- to bus
			readdata:		out std_logic_vector( 15 downto 0 )	-- to bus
		);
	end component;
	
	signal t_vd_ena:		std_logic;	-- vga_ctrl to vga_display
	signal t_vd_data:		std_logic_vector( 15 downto 0 ); -- vga_ctrl to vga_display
	signal t_vd_addr:		std_logic_vector( 16 downto 0 ); -- vga_display to vga_ctrl
	signal t_vd_read_n:		std_logic;	-- vga_display to vga_ctrl
	signal t_vd_be_n:		std_logic_vector( 1 downto 0 ); -- vga_display to vga_ctrl
	signal t_inuse:			std_logic;	-- vga_display to vga_ctrl
	signal t_scan:			std_logic;	-- vga_display to vga_ctrl
	
begin
	
	Vga_display_inst: vga_display
		port map
		(
			clk			=>	clk_vga,
			ena			=>	t_vd_ena,
			data		=>	t_vd_data,
			addr		=>	t_vd_addr,
			read_n		=>	t_vd_read_n,
			be_n		=>	t_vd_be_n,
			inuse		=>	t_inuse,
			scan		=>	t_scan,
			vga_sync	=>	vga_sync,
			vga_hsync	=>	vga_hsync,
			vga_vsync	=>	vga_vsync,
			vga_blank	=>	vga_blank,
			vga_r		=>	vga_r,
			vga_g		=>	vga_g,
	--------------- for debug ---------------------
	--		ohodd:		out std_logic;
	--		ovodd:		out std_logic;
	--		ohscan:		out std_logic;
	--		ovscan:		out std_logic;
	--		ohcnt:		out integer range 0 to 799;
	--		ovcnt:		out integer range 0 to 525;
	-----------------------------------------------
			vga_b		=>	vga_b
		);
	
	Vga_ctrl_inst: vga_ctrl
		port map
		(
			clk				=>	clk,
			reset			=>	reset,
			chipselect		=>	chipselect,
			address			=>	address,
			read_n			=>	read_n,
			write_n			=>	write_n,
			writedata		=>	writedata,
			byteenable_n	=>	byteenable_n,
			vd_inuse		=>	t_inuse,
			vd_scan			=>	t_scan,
			vd_addr			=>	t_vd_addr,
			vd_read_n		=>	t_vd_read_n,
			vd_be_n			=>	t_vd_be_n,
			sram_dq			=>	sram_dq,
			sram_addr		=>	sram_addr,
			sram_we_n		=>	sram_we_n,
			sram_oe_n		=>	sram_oe_n,
			sram_ub_n		=>	sram_ub_n,
			sram_lb_n		=>	sram_lb_n,
			sram_ce_n		=>	sram_ce_n,
			vd_ena			=>	t_vd_ena,
			vd_data			=>	t_vd_data,
			waitrequest		=>	waitrequest,
			readdata		=>	readdata
		);
	
end RTL;