📄 sd_wr.vhd
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stat_next <= SD_WR_RECV_R1b_TO_CMD12;
end if;
when SD_WR_STRRECV_PAUSE =>
if( traceaddr = '0' ) then
stat_next <= SD_WR_IDLE;
else
if( wrusedw <= WRITE_TH ) then
stat_next <= SD_WR_SEND_CMD18;
else
stat_next <= SD_WR_STRRECV_PAUSE;
end if;
end if;
when others =>
stat_next <= SD_WR_INIT;
end case;
end process Stat_next_P;
Stream_read: process( clk, stat, readm_r, dataaddr_r, traceaddr )
begin
if( rising_edge( clk ) ) then
if( readm_r = '0' ) then
traceaddr <= '0';
else
traceaddr <= traceaddr;
end if;
straddr <= straddr;
case stat is
when SD_WR_INIT =>
traceaddr <= '0';
when SD_WR_REC_ADDR=>
traceaddr <= '1';
straddr <= dataaddr_r;
when SD_WR_INC_ADDR =>
straddr <= conv_std_logic_vector( conv_integer(straddr) + 1, straddr'length );
when others =>
end case;
end if;
end process Stream_read;
Cnt_q_P: process( clk, stat, cnt_d )
begin
if( rising_edge( clk ) ) then
case stat is
when SD_WR_PRE_WAIT_PWRUP =>
cnt_q <= 80;
when SD_WR_PRE_WAIT_READY =>
cnt_q <= 127;
when others =>
cnt_q <= cnt_d;
end case;
end if;
end process Cnt_q_P;
Cnt_d_P: process( cnt_q )
begin
if( cnt_q > 0 ) then
cnt_d <= cnt_q - 1;
else
cnt_d <= 0;
end if;
end process Cnt_d_P;
RCA_P: process( clk, stat, rr_content, RCA )
begin
if( rising_edge( clk ) ) then
if( stat = SD_WR_RECORD_RCA ) then
RCA <= rr_content( 31 downto 16 );
else
RCA <= RCA;
end if;
end if;
end process RCA_P;
Mux: process( stat, sc_q, sd_cmd, sd_data )
begin
-- sd_cmd: inout std_logic; -- sd cmt
-- sd_data: inout std_logic; -- sd data0
-- sd_data3: inout std_logic; -- sd data3
-- sc_q: in std_logic; -- from sendcmd
-- rr_cmd: out std_logic -- to recvresp
sd_cmd <= 'Z';
sd_data <= "ZZZZ";
rr_cmd <= '1';
rd_data <= X"F";
case stat is
when SD_WR_INIT =>
when SD_WR_IDLE =>
-- reset the card
when SD_WR_PRE_WAIT_PWRUP =>
when SD_WR_WAIT_PWRUP =>
when SD_WR_SEND_CMD0 =>
sd_data(3) <= '1';
sd_cmd <= sc_q;
-- wait for the card to be ready
when SD_WR_PRE_WAIT_READY =>
sd_data(3) <= '1';
when SD_WR_WAIT_READY =>
sd_data(3) <= '1';
when SD_WR_SEND_CMD55 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R1_TO_CMD55 =>
rr_cmd <= sd_cmd;
when SD_WR_SEND_ACMD41 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R3_TO_ACMD41 =>
rr_cmd <= sd_cmd;
-- continue init the card
when SD_WR_SEND_CMD2 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R2_TO_CMD2 =>
rr_cmd <= sd_cmd;
when SD_WR_SEND_CMD3 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R6_TO_CMD3 =>
rr_cmd <= sd_cmd;
when SD_WR_RECORD_RCA =>
when SD_WR_SEND_CMD9 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R2_TO_CMD9 =>
rr_cmd <= sd_cmd;
when SD_WR_SEND_CMD7 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R1_TO_CMD7 =>
rr_cmd <= sd_cmd;
-- set 4 line mode
when SD_WR_SEND_CMD55_2 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R1_TO_CMD55_2 =>
rr_cmd <= sd_cmd;
when SD_WR_SEND_ACMD6 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R1_TO_ACMD6 =>
rr_cmd <= sd_cmd;
-- set block length
when SD_WR_SEND_CMD16 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R1_TO_CMD16 =>
rr_cmd <= sd_cmd;
-- init finished
when SD_WR_INIT_FAILED =>
when SD_WR_INIT_SUCCESS =>
-- read card
when SD_WR_SEND_CMD17 =>
sd_cmd <= sc_q;
when SD_WR_RECV_DATA =>
rd_data <= sd_data;
when SD_WR_SEND_CMD18 =>
sd_cmd <= sc_q;
when SD_WR_STRRECV_DATA =>
rd_data <= sd_data;
when SD_WR_SEND_CMD12 =>
sd_cmd <= sc_q;
when SD_WR_RECV_R1b_TO_CMD12 =>
rr_cmd <= sd_cmd;
when others =>
end case;
end process Mux;
Output: process( stat, RCA, dataaddr_r, straddr )
begin
sc_send <= '0';
sc_cmdno <= ( others => '0' );
sc_content <= ( others => '0' );
rr_recv <= '0';
rr_longresp <= '0';
rd_recv <= '0';
case stat is
when SD_WR_INIT =>
when SD_WR_IDLE =>
-- reset the card
when SD_WR_PRE_WAIT_PWRUP =>
when SD_WR_WAIT_PWRUP =>
when SD_WR_SEND_CMD0 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 0, sc_cmdno'length );
-- wait for the card to be ready
when SD_WR_PRE_WAIT_READY =>
when SD_WR_WAIT_READY =>
when SD_WR_SEND_CMD55 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 55, sc_cmdno'length );
when SD_WR_RECV_R1_TO_CMD55 =>
rr_recv <= '1';
rr_longresp <= '0';
when SD_WR_SEND_ACMD41 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 41, sc_cmdno'length );
sc_content <= X"0ff00000";
when SD_WR_RECV_R3_TO_ACMD41 =>
rr_recv <= '1';
rr_longresp <= '0';
-- continue init the card
when SD_WR_SEND_CMD2 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 2, sc_cmdno'length );
when SD_WR_RECV_R2_TO_CMD2 =>
rr_recv <= '1';
rr_longresp <= '1';
when SD_WR_SEND_CMD3 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 3, sc_cmdno'length );
when SD_WR_RECV_R6_TO_CMD3 =>
rr_recv <= '1';
rr_longresp <= '0';
when SD_WR_RECORD_RCA =>
when SD_WR_SEND_CMD9 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 9, sc_cmdno'length );
sc_content( 31 downto 16 ) <= RCA;
when SD_WR_RECV_R2_TO_CMD9 =>
rr_recv <= '1';
rr_longresp <= '1';
when SD_WR_SEND_CMD7 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 7, sc_cmdno'length );
sc_content( 31 downto 16 ) <= RCA;
when SD_WR_RECV_R1_TO_CMD7 =>
rr_recv <= '1';
rr_longresp <= '0';
-- set 4 line mode
when SD_WR_SEND_CMD55_2 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 55, sc_cmdno'length );
sc_content( 31 downto 16 ) <= RCA;
when SD_WR_RECV_R1_TO_CMD55_2 =>
rr_recv <= '1';
rr_longresp <= '0';
when SD_WR_SEND_ACMD6 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 6, sc_cmdno'length );
sc_content( 1 downto 0 ) <= "10";
when SD_WR_RECV_R1_TO_ACMD6 =>
rr_recv <= '1';
rr_longresp <= '0';
-- set block length
when SD_WR_SEND_CMD16 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 16, sc_cmdno'length );
sc_content <= conv_std_logic_vector( BLOCK_LEN, sc_content'length );
when SD_WR_RECV_R1_TO_CMD16 =>
rr_recv <= '1';
rr_longresp <= '0';
-- init finished
when SD_WR_INIT_FAILED =>
when SD_WR_INIT_SUCCESS =>
-- read card
when SD_WR_SEND_CMD17 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 17, sc_cmdno'length );
sc_content <= dataaddr_r( 31 - BLOCK_LEN_LOG2 downto 0 ) & conv_std_logic_vector( 0, BLOCK_LEN_LOG2 );
when SD_WR_RECV_DATA =>
rd_recv <= '1';
when SD_WR_SEND_CMD18 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 18, sc_cmdno'length );
sc_content <= straddr( 31 - BLOCK_LEN_LOG2 downto 0 ) & conv_std_logic_vector( 0, BLOCK_LEN_LOG2 );
when SD_WR_STRRECV_DATA =>
rd_recv <= '1';
when SD_WR_SEND_CMD12 =>
sc_send <= '1';
sc_cmdno <= conv_std_logic_vector( 12, sc_cmdno'length );
when SD_WR_RECV_R1b_TO_CMD12 =>
rr_recv <= '1';
rr_longresp <= '0';
when others =>
end case;
end process Output;
Async_output: process( clk, stat, cardready_r )
begin
if( rising_edge( clk ) ) then
buzy_r <= '1';
cardready_r <= cardready_r;
aclr <= '0';
case stat is
when SD_WR_INIT =>
cardready_r <= '0';
aclr <= '1';
when SD_WR_IDLE =>
buzy_r <= '0';
-- init finished
when SD_WR_INIT_FAILED =>
cardready_r <= '0';
when SD_WR_INIT_SUCCESS =>
cardready_r <= '1';
when SD_WR_CLEAR_BUFFER =>
aclr <= '1';
when others =>
end case;
end if;
end process Async_output;
buzy <= buzy_r;
cardready <= cardready_r;
--------------- for debug ---------------------
-- ostat <= stat;
-----------------------------------------------
end RTL;
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