sendcmd.vhd

SD卡读卡器模块的VHDL及软件驱动代码

library IEEE;
use IEEE.std_logic_1164.all;
use WORK.pck_CRC7.all;

entity sendcmd is
	port
	(
		clk:		in std_logic;	-- sd clk
		areset:		in std_logic;	-- async reset
		send:		in std_logic;	-- send request
		cmdno:		in std_logic_vector( 5 downto 0 ); -- cmd number
		content:	in std_logic_vector( 31 downto 0 ); -- cmd content
		buzy:		out std_logic;	-- buzy sending
-------- for debug ---------------
--		ocnt:		out integer range 0 to 39;
--		ocmd:		out std_logic_vector( 39 downto 0 );
--		ocrc:		out std_logic_vector( 6 downto 0 );
------------------------------------
		q:			out std_logic	-- to sd cmd
	);
end sendcmd;

architecture RTL of sendcmd is
	
	type SC_STAT is
	(
		SC_IDLE,
		SC_PREWAIT,	-- pre-wait 7 cyc (only load counter)
		SC_WAIT,	-- wait 7 cyc
		SC_PREPARE, -- prepare to send cmd (only load counter)
		SC_SENDCMD, -- send cmd
		SC_PRESENDCRC, -- pre-send crc (load counter and send first bit)
		SC_SENDCRC, -- send crc
		SC_FINISH, -- finished sending
		SC_WAITRECV -- wait for "send" become low
	);
	
	signal stat:		SC_STAT;
	signal stat_next:	SC_STAT;
	signal cmd:			std_logic_vector( 39 downto 0 ); -- latch
	signal cnt_q:		integer range 0 to 39;
	signal cnt_d:		integer range 0 to 39;
	signal crc:			std_logic_vector( 6 downto 0 );
	signal crc_next:	std_logic_vector( 6 downto 0 );
	
begin
	
	Stat_P: process( clk, areset, stat_next )
	begin
		if( areset = '1' ) then
			stat <= SC_IDLE;
		elsif( rising_edge( clk ) ) then
			stat <= stat_next;
		end if;
	end process Stat_P;
	
	Stat_next_P: process( stat, send, cnt_q )
	begin
		case stat is
			
			when SC_IDLE =>
				if( send = '1' ) then
					stat_next <= SC_PREWAIT;
				else
					stat_next <= SC_IDLE;
				end if;
			
			when SC_PREWAIT =>
				stat_next <= SC_WAIT;
			
			when SC_WAIT =>
				if( cnt_q = 0 ) then
					stat_next <= SC_PREPARE;
				else
					stat_next <= SC_WAIT;
				end if;
			
			when SC_PREPARE =>
				stat_next <= SC_SENDCMD;
			
			when SC_SENDCMD =>
				if( cnt_q = 0 ) then
					stat_next <= SC_PRESENDCRC;
				else
					stat_next <= SC_SENDCMD;
				end if;
			
			when SC_PRESENDCRC =>
				stat_next <= SC_SENDCRC;
			
			when SC_SENDCRC =>
				if( cnt_q = 0 ) then
					stat_next <= SC_FINISH;
				else
					stat_next <= SC_SENDCRC;
				end if;
			
			when SC_FINISH =>
				if( send = '1' ) then
					stat_next <= SC_WAITRECV;
				else
					stat_next <= SC_IDLE;
				end if;
			
			when SC_WAITRECV =>
				if( send = '1' ) then
					stat_next <= SC_WAITRECV;
				else
					stat_next <= SC_IDLE;
				end if;
			
			when others =>
				stat_next <= SC_IDLE;
			
		end case;
	end process Stat_next_P;
	
	Cmd_P: process( clk, send, cmd )
	begin
		if( rising_edge( clk ) ) then
			if( send = '1' ) then
				cmd <= '0' & '1' & cmdno & content;
			else
				cmd <= cmd;
			end if;
		end if;
	end process Cmd_P;
	
	Cnt_q_P: process( clk, stat, cnt_d )
	begin
		if( rising_edge( clk ) ) then
			case stat is
				
				when SC_PREWAIT =>
					cnt_q <= 6;
				
				when SC_PREPARE =>
					cnt_q <= 39;
				
				when SC_PRESENDCRC =>
					cnt_q <= 6 - 1;
				
				when others =>
					cnt_q <= cnt_d;
				
			end case;
		end if;
	end process Cnt_q_P;
	
	Cnt_d_P: process( cnt_q )
	begin
		if( cnt_q > 0 ) then
			cnt_d <= cnt_q - 1;
		else
			cnt_d <= 0;
		end if;
	end process Cnt_d_P;
	
	Crc_P: process( clk, stat, crc_next )
	begin
		if( rising_edge( clk ) ) then
			case stat is
				
				when SC_PREPARE =>
					crc <= ( others => '0' );
				
				when SC_SENDCMD =>
					crc <= crc_next;
				
				when others =>
					crc <= crc;
				
			end case;
		end if;
	end process Crc_P;
	
	Crc_next_P: process( cmd, cnt_q, crc )
	begin
		crc_next <= nextCRC7( cmd(cnt_q), crc );
	end process Crc_next_P;
	
	Output: process( stat, cmd, cnt_q, crc )
	begin
		
		buzy <= '0';
		q <= '1';
		
		case stat is
			
			when SC_PREWAIT =>
				buzy <= '1';
				
			when SC_WAIT =>
				buzy <= '1';
			
			when SC_PREPARE =>
				buzy <= '1';
			
			when SC_SENDCMD =>
				buzy <= '1';
				q <= cmd( cnt_q );
			
			when SC_PRESENDCRC =>
				buzy <= '1';
				q <= crc( 6 );
			
			when SC_SENDCRC =>
				buzy <= '1';
				q <= crc( cnt_q );
			
			when SC_FINISH =>
				buzy <= '1';
				q <= '1';
			
			when others =>
			
		end case;
		
	end process Output;
	
---------- for debug ---------------
--	ocnt <= cnt_q;
--	ocmd <= cmd;
--	ocrc <= crc;
------------------------------------
	
end RTL;