ati.txt

比较详尽的VGA端口寄存器的文档

A2EEh W(R/W):  Linedraw Options Register                            (Mach8/32)
bit    1  POLY_MODE. Clear for normal linedraw, set for polygon linedraw mode.
       2  LAST_PEL_OFF. Set if the last pixel of a line should not be drawn.
       3  DIR_TYPE. If set lines are drawn in the direction set by bits 5-7
          and of the length in the Bresenham Count Register (96EEh), if clear
          according to the Bresenham parameters
     5-7  (bit 3=1) DEGREE. Direction of the line in degrees
            0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315
       5  (bit 3=0) XDIR.  Set to draw to the right (increase X)
       6  (bit 3=0) YMAJOR. Set if delta Y > delta X (numerically)
       7  (bit 3=0) YDIR. Set to draw downwards (increase Y)
       8  BOUNDS_RESET. If set the accumulator registers are reset to
            Left=2047, Top=2047, Right=-2048, Bottom=-2048
    9-10  CLIP_MODE.
            0: Clip exception disabled
            1: Stroked line segments
            2: Polygon boundary lines
            3: Patterned lines

A6EEh W(W):  Destination Start X Register                           (Mach8/32)
bit 0-10  DEST_X_START. Starting X coordinate for the destination blit

AAEEh W(W):  Destination X End Register                             (Mach8/32)
bit 0-10  DEST_X_END. Ending X coordinate of each row of the destination blit

AEEEh W(W):  Destination Y End Register                             (Mach8/32)
bit 0-10  DEST_Y_END. Ending line of the destination blit for VRAM to VRAM

B2EEh W(R):  R Horizontal Displayed & Total Register                  (Mach32)
bit  0-7  H_DISP. Pixels displayed horizontally, in units of 8 pixels.
          This field is written at 6E8h
    8-15  H_TOTAL. Total horizontal screen width in units of 8 pixels.
          This field is written at 2E8h

B2EEh W(W):  Source X Start Register                                (Mach8/32)
bit 0-10  SRC_X_START. First pixel of the blit area (except first row)

B6EEh (R):  Horizontal Sync Start Register                            (Mach32)
bit  0-7  H_SYNC_STRT. HSync start in units of 8 pixels.
Note: This register is written at 0AE8h

B6EEh (W):  Background Function Register                            (Mach8/32)
bit  0-4  ALU_BG_FN. Background ALU function code

BAEEh (R):  Horizontal Sync Width Register                            (Mach32)
bit  0-4  H_WIDTH. Width of the sync in units of 8 pixels
       5  H_POLARITY. Set for negative Horizontal sync polarity, clear for
          positive Horizontal sync
Note: This register is written at 0EE8h

BAEEh (W):  Foreground Function Register                            (Mach8/32)
bit  0-4  ALU_FG_FN. Foreground ALU function code.

BEEEh W(W):  Source X End Register                                  (Mach8/32)
bit 0-10  SRC_X_END. Last pixel of the blit source area

C2EEh W(R):  Vertical Total Register                                  (Mach32)
bit 0-11  V_TOTAL. Total number of scanlines in a frame.
Note: This register is written at 12E8h

C2EEh (W):  Source Y Direction Register                             (Mach8/32)
bit    0  SRC_Y_DIR. Direction of drawing. Set for top-to-bottom, clear for
          bottom-to-top.

C6EEh W(R):  Vertical Displayed Register                              (Mach32)
bit 0-11  V_DISP. Number of scanlines displayed (-1).
Note: This register is written at 16E8h

C6EEh W(W):  Extended Short Stroke Vector Transfer Register         (Mach8/32)
bit  0-3  Length of the major axis
       4  Set for drawing, clear for moves
     5-7  Direction in degrees:
            0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315
    8-15  Same as bits 0-7, but another vector.
Note: this is similar to 9EE8h

CAEEh W(R):  Vertical Sync Start Register                             (Mach32)
bit 0-11  V_SYNC_STRT. Vertical sync start in scanlines
Note: This register is written at 1AE8h

CAEEh W(W):  Scan To X Register                                      (Mach8/32
bit 0-10  SCAN_TO_X. Can be used for fast polygon scan conversion and
          horizontal lines. Drawn from current X position to this position.
          Left edge drawn, right edge not drawn.

CEEEh W(R):  Vertical Line Counter Register                           (Mach32)
bit 0-10  VERT_LINE_CNTR. Vertical Line Counter

CEEEh W(W):  Data Path Configuration Register                       (Mach8/32)
bit    0  READ_WRITE. If set data is written to the drawing trajectory, if
          clear read from it.
       1  POLY_FILL_MODE. If set Polygon-fill blit mode is enabled, blit
          source mechanism is triggered and VRAM source blit data is used as
          the polygon fill mask, if clear polygon-fill blit mode is disabled
          Cleared at the start of each row of the blit.
       2  READ_MODE. If set read host data is monochrome, if clear color.
       4  DRAW. Enable Draw if set.
     5-6  MONO_SRC. Monochrome source is:
            0: Always "1"
            1: Mono Pattern register
            2: Pixel Transfer register
            3: VRAM blit source
     7-8  BG_COLOR_SRC. Background Color Source select.
            0: Background color register
            1: Foreground color register
            2: Pixel transfer register
            3: VRAM blit source
       9  DATA_WIDTH. Width of the data transferred through the CPU Data
          Transfer register. 0: 8bit, 1: 16bit
          Should be set in 16bit/pixel modes.
      12  LSB_FIRST. If set the CPU Data Transfer register is "Intel little
          endian style" (least significant byte first), if clear in "Motorola
          big endian style" (most significant byte first).
          In Mach8 mode this bit is ignored if bit 9 is 0.
   13-15  FG_COLOR_Src. Foreground color source select.
            0: Background color register
            1: Foreground color register
            2: Pixel transfer register
            3: VRAM blit source
            5: Color pattern shift register

D2EEh W(R):  Vertical Sync Width Register                             (Mach32)
bit  0-4  V_WIDTH. Width of Vsync pulse in scanlines
       5  V_POLARITY. Set for negative Vsync, clear for positive Vsync
Note: This register is written at 1EE8h

D2EEh W(W):  Pattern Length Register                                (Mach8/32)
bit  0-4  PATT_LENGTH. Number of pixels (-1) in the pattern
       7  8x8 Mono Pattern Enable. If set bits 0-4 are ignored and Pattern
          Data index 10h-17h are used as an 8x8 rectangular pattern
      15  8x8 Block Write Mono Pattern Enable. If set the 8x8 pattern
          described in bit 7 is used as a transparency mask for the write

D6EEh (W):  Pattern Index Register                                  (Mach8/32)
bit  0-4  PATT_INDEX. Selects the first pixel in the color or mono pattern for
          the destination

DAEEh W(R):  Read Source X Register                                 (Mach8/32)
bit 0-10  R_SRC_X. Source current X. This register is written at 8EE8h

DAEEh W(W):  Extended Left Scissor Register                         (Mach8/32)
bit 0-11  EXT_SCISSOR_L. Left scissor (-2048..2047)

DEEEh W(R):  Read Source Y Register                                 (Mach8/32)
bit 0-10  R_SRC_Y. Source current Y. This register is written at 8AE8h

DEEEh W(W):  Extended Top Scissor Register                          (Mach8/32)
bit 0-11  EXT_SCISSOR_T. Top scossor (-2048..2047)

E2EEh W(W):  Extended Right Scissor Register                        (Mach8/32)
bit 0-11  EXT_SCISSOR_R. Right scissor (-2048..2047)

E6EEh W(W):  Extended Bottom Scissor Register                       (Mach8/32)
bit 0-11  EXT_SCISSOR_B. Bottom Scissor (-2048..2047)

EEEEh W(W):  Destination Color Compare Function Register            (Mach8/32)
bit  3-5  DEST_CMP_FN_4/8. 4/8bit mode destination compare function code
            0:  False
            1:  True
            2:  Destination pixel >= DEST_CMP_CLR
            3:  Destination pixel <  DEST_CMP_CLR
            4:  Destination pixel != DEST_CMP_CLR
            5:  Destination pixel =  DEST_CMP_CLR
            6:  Destination pixel <= DEST_CMP_CLR
            7:  Destination pixel >  DEST_CMP_CLR
          The pixels where the comparison is true are NOT updated.
     6-8  DEST_CMP_FN_B. 16bit blue destination compare function code
    9-11  DEST_CMP_FN_G. 16bit green destination compare function code
   12-14  DEST_CMP_FN_R. 16bit red destination compare function code

F2EEh W(R/W):  Destination Color Compare Function Register         (68800-6 +)
bit 0-15  Destination Color Compare Mask

FAEEh W(R):  Chip ID Register                                      (68800-6 +)
bit 0-9  CHIP_CODE. Identifies the chip version:
           017h  68800-AX
           177h  68800-LX
           2F7h  68800-6
         The 68800-3 appears to return 0 for this field (undocumented)
  10-11  CHIP_CLASS.
  12-15  CHIP_REV.

FEEEh W(W):  Linedraw Register                                      (Mach8/32)
bit 0-15  Line data. 9AEEh determines which type of line data is written



Bank Switching

  Bank switching can use either one single bank register or two
  separate read and write bank registers (18800-2 and 28800 Only).
  Banks map to 64k boundaries.

Reserved locations in the ROM (typically starting at C000h:0):

  $10   2 bytes   ATI Register (usually $1CE).
  $31   9 bytes   '761295520' ID's ATI product
  $40   2 bytes   '31' = ATI VGA Wonder/Mach series
                  '32' = ATI EGA Wonder 800+
                  '34' = ATI VGA Basic-16
                  '22' = ATI EGA Wonder
                 ?+'3' = ATI Basic-16
  $42   1 byte    Bit 0  Set for 16-bit boards
                      1  Mouseport present if set
                      2  Use hardware detection to detect mouse port if set
                      3  Microchannel if set, PC/AT else
                      4  Use clock chip if set
                      7  Use C000:0000 to D000:FFFF with 16 bit ROM if set
  $43   1 byte    Gate revision.
                   ' ' (20h) = Mach64 (see Mach64 section below)
                   '1' (31h) = 18800   (V3),
                   '2' (32h) = 18800-1 (V4/V5),
                   '3' (33h) = 28800-2  VGA Wonder+ (V6).
                   '4' (34h) = 28800-4  VGA Wonder (1MB)
                   '5' (35h) = 28800-5  VGA Wonder 1MB/XL
                   '6' (36h) = 28800-6  VGA Wonder XL
                   'a' (61h) = 68800    Mach-32
                   'c' (63h) = 68800    Mach-32 - Which version ?
  $44   1 byte    Bit 0  If clear the board can support 70Hz
                         non-interlaced refresh
                      1  If set the board supports Korean characters in VGA
                         mode
                      2  If set the board uses 45MHz memory clock, if clear
                         40MHz
                      3  If clear the board supports zero wait states.
                      4  If set the board uses paged ROMs.
                      6  If clear there is 8514/A hardware on board (Graphics
                         Ultra)
                      7  If set there is a 32K color DAC on board.
  $4C   1 byte    Major Bios version
  $4D   1 byte    Minor Bios version

  $64  (Mach32) Far call entry point to Load Shadow Set function
       AH = 0
  $68  (Mach32) Far call entry point to Set Mode function
       AL = 00h  Load VGA passthrough mode
            01h  Load low resolution mode
            02h  Load high resolution mode

  $6C  (Mach32) Far call entry point to Query function
       AL = 00h  Query information structure in bytes
                 Returns size in AX
            01h  Query device long
                 ES:BX -> Device Status Table to be filled out
                 OFFSET  TYPE   Description:
                   00h   WORD   Size of structure in bytes
                   02h   BYTE   Revision of structure
                   03h   BYTE   Number of mode tables
                   04h   WORD   Offset of mode tables
                   06h   BYTE   Size of mode tables in bytes
                   07h   BYTE   ASIC Revision
                   08h   BYTE   Sta