ati.txt

比较详尽的VGA端口寄存器的文档

       2  LOCK_H_PARAMS. Locks the Horizontal Sync parameters: Position, Width
          and Total.
       3  LOCK_H_DISP. Locks Horizontal Displayed
       4  LOCK_V_PARAMS. Locks Vertical Sync parameters: Width, Start and
          Total.
       5  LOCK_V_DISP. Locks Vertical Displayed
       6  (Mach32) LOCK_OVERSCAN. Locks the selection of shadow overscan
            register set in 1024x768 resolution.

4AEEh W(R/W):  Clock Select Register                                (Mach8/32)
bit    0  PASS_THROUGH. If set video output id's from the 8514, if clear from
          either the internal VGA or from the Feature Connector.
     2-5  CLK_SEL. Clock Select lines to the 1881x clock chip.
       6  CLK_DIV. If set divide clock by 2.
       7  Refresh. Enables video memory refresh counter if clear.
    8-11  VFIFO_DEPTH. When the Video FIFO has less than this number of
          entries refill will start. Only used for DRAM systems, however
          performance at high resolutions can be optimized regardlessly.
      12  COMPOSITE_SYNC.
          (Mach8) If set Composite Sync used with the primary CRT register
            set, if clear Composite Sync used when programming CRT Shadow Set
            1 or 2.
          (Mach32) Set for Composite Sync, clear for separate Sync.
Note: in Mach8 mode this register is Read Only.
      Writing to this register switches the CRT controller to ATI mode,
      writing to 4AE8h switches to 8514 mode.

52EEh W(R/W):  Scratch Pad 0 Register                                 (Mach32)
bit  0-6  ROM address: 0: C000h, 1: C080h, 2: C100h ...
    8-15  Scratch Pad

56EEh W(R/W):  Scratch Pad 1 Register                                 (Mach32)
bit 0-15  Scratch Pad

5AEEh W(W):  Shadow Set Register                                    (Mach8/32)
bit  0-1  SHADOW_SET. Selects the current CRT register set:
            0: Primary CRT register set
            1: Shadow set 1 (usually 640x480)
            2: Shadow set 2 (usually 1024x768)
     8-9  (68800-6 +) LOAD_SRC/DST. Determines whether the source and
            destination offset/pitch registers are loaded together:
             0: Load Destination and Source Offset/Pitch registers together
             1: Load Destination Offset/Pitch register only
             2: Load Source Offset/Pitch register only

5EEEh W(R/W):  Memory Aperture Configuration Register                 (Mach32)
bit  0-1  MEM_APERT_SEL. Aperture: 0: Disabled, 1: 1MB, 2: 4MB
          PCI configuration does not support 1MB aperture
     2-3  MEM_APERT_PAGE. Memory aperture page selection in 1MB aperture mode.
    4-15  MEM_APERT_LOC. Address of aperture in 1MB steps between 0 and 4GB
    8-15  MEM_APERT_LOC. Address of aperture in 1MB steps between 0 and 128MB
Note: bit 8-15 is used as the Aperture Address except for PCI systems and
      multiplexed local bus systems (16EEh bit 13 set) where bit 4-15 are used

62EEh W(R):  Extended Graphics Engine Status Register                 (Mach32)
bit  0-3  CLIP_OVERRUN. Clip Overrun
       8  CLIP_INSIDE. Clip Inside
    9-12  CLIP_FLAGS. For each bit: 0: outside scissor, 1: inside ?
      13  GE_ACTIVE. The Graphics Engine is busy if set.
      14  EE_DATA_IN. EEProm data in
      15  POINTS_OUTSIDE. Points Outside.

62EEh W(W):  Horizontal Overscan Register                             (Mach32)
bit  0-3  Overscan Width - left side in character units
     4-7  Overscan Width - right side in character units
    8-10  (68800-6 +) H_SYNC_DELAY. Horizontal Sync Delay in pixels (for
            1280x1024 multiplexed pixel modes in units of 2 pixels)
      12  (68800-6 +) OSCAN_INV. Inverts Overscan Polarity if set
      13  (68800-6 +) SYN_CONT_SEL. If set bits 14-15 controls HSYNC and VSYNC
      14  (68800-6 +) HSYN_CONT. If bit 13 is set this bit controls the HSYNC
            signal
      15  (68800-6 +) VSYN_CONT. If bit 13 is set this bit controls the VSYNC
            signal

66EEh W(W):  Vertical Overscan Register                               (Mach32)
bit  0-7  Overscan height - top in lines
    8-15  Overscan height - bottom in lines

6AEEh W(R/W):  Maximum Wait-States Register              (Mach8, 68800-3/6/LX)
bit  0-3  Q_WSTATES. Max number of wait-states (in units of 0.25 clocks) that
          the engine can generate during I/O writes. 0 = No Wait states
          Set to 0Ch on hardware reset
     4-7  ROM_SPEED. Number of wait states inserted by the engine when the ROM
          BIOS is read. Set to 0Fh on hardware reset. 0 = No Wait states.
       8  LINE_OPT_ENA. Horizontal Line draw optimisations enabled if clear.
          Must be disabled during degree-mode linedraws to keep the ERR_TERM
          register 8514 compatible.
       9  (Mach8) IOR16_ENA. 16bit I/O reads enabled if clear.
      10  (Mach8) PASSTHROUGH_OVERRIDE. Clear if passthrough connection made,
            set if not (no VGA sync detected). Must be set correctly for the
            DAC to function.

6AEEh W(R/W):  Memory Aperture Configuration Register               (68800-AX)
bit   10  F_APERT_ENA. Enables zero waitstate aperture write if set
      11  FIFO_RD_AHEAD. Enables Read Ahead for aperture read operation if set
          Speeds up sequential reads
      12  SCLK_DLY. Pixel Stream 1 SCLK Delay if set
      13  DEC_BURST_ENA. Enables Decrement Burst if set
      14  INC_BURST. Increments Burst if set, decrements if clear
      15  PCI_TIMEOUT_DIS. Enables bus timeout on burst read/writes if clear
Note: This register available in PCI configurations only

6EEEh W(W):  Graphics Engine Offset Low Register                    (Mach8/32)
bit 0-15  Lower bits of the Graphics Engine Offset. Upper bits are in 72EEh.
          Video buffer address in units of 4 bytes

72EEh W(R):  Bounds Accumulator Left Register                       (Mach8/32)
bit 0-15  BOUNDS_LEFT. The lowest X coordinate written through the linedraw
          register. Reset to 2047 when A2EEh bit 8 is set

72EEh (W):  Graphics Engine Offset High Register                    (Mach8/32)
bit  0-3  Upper 4 bits of the Graphics Engine Offset. Lower bits are in 6EEEh

76EEh W(R):  Bounds Accumulator Top Register                        (Mach8/32)
bit 0-15  BOUNDS_TOP. The lowest X coordinate written through the linedraw
          register. Reset to 2047 when A2EEh bit 8 is set

76EEh (W):  Graphics Engine Pitch Register                          (Mach8/32)
bit  0-7  GE_PITCH. Width of the display buffer in units of 8 pixels.

7AEEh (W):  Extended Graphics Engine Configuration Register            (Mach8)
bit    0  EE_DATA_OUT
       1  EE_CLK
       2  EE_CS
       3  ALIAS_ENA
       4  Z1280
       7  EE_SELECT
Note: This register is used in 8bit mode (card in an 8bit slot or the 8/16bit
      jumper set for 8bit)

7AEEh W(R):  Bounds Accumulator Right Register                      (Mach8/32)
bit 0-15  BOUNDS_RIGHT. The highest X coordinate written through the linedraw
          register. Reset to -2048 when A2EEh bit 8 is set

7AEEh W(W):  Extended Graphics Engine Configuration Register        (Mach8/32)
bit  0-2  MONITOR_ALIAS. Alternate monitor ID for 8514/A application use
       3  ALIAS_ENA. If set read of the Subsystem Status register (42E8h)
          returns the monitor ID in bit 0-2 rather than the actual ID.
     4-5  (Mach32) PIXEL_WIDTH. Number of bits per pixel
              0: 4bits/pixel(bpp), 1: 8bpp, 2: 16bpp, 3: 24bpp
            16 and 24 bits per pixel only supported if we have at least 1MB
            and the DAC can handle it.
     6-7  (Mach32) 16_BIT_COLOR_MODE. 16bit pixel format:
            0: (5,5,5) Red = bit 10-14, Green = bit  5-9, Blue = bit 0-4
            0: (5,6,5) Red = bit 11-15, Green = bit 5-10, Blue = bit 0-4
            0: (6,5,5) Red = bit 10-15, Green = bit  5-9, Blue = bit 0-4
            0: (6,6,4) Red = bit 10-15, Green = bit  4-9, Blue = bit 0-3
       8  (Mach32) MULTIPLEX_PIXELS. If set 4 pixels are sent to the DAC in
            parallel
       9  (Mach32) 24_BIT_COLOR_CONFIG. If set 24bit pixel occupy 4 bytes and
            bit 10 selects the unused byte within the pixel, if clear 24bit
            pixel occupy 3 bytes.
      10  (Mach32) 24_BIT_COLOR_ORDER. Selects the order the colors are stored
            in 24bit pixels. If set Red is stored first, if clear blue first.
             Bit10  Bit9    Red     Green    Blue
               0      0   Byte 2   Byte 1   Byte 0
               0      1   Byte 3   Byte 2   Byte 1
               1      0   Byte 0   Byte 1   Byte 2
               1      1   Byte 0   Byte 1   Byte 2
      11  (68800-6 +) DISPLAY_PIXEL_SIZE. Set to load display pixel size.
            If both bit 11 and 15 are 0 both pixel sizes are loaded
   12-13  (Mach32) DAC_EXT_ADDR. Connected to RS2 and RS3 on the DAC.
      12  (Mach8) EE_DATA_OUT. Data output for the EEPROM
      13  (Mach8) EE_CLK. Clock signal for the EEPROM
      14  (Mach32) DAC_8_BIT_EN. Set for 8bit DAC operation, clear for 6bit
          (Mach8) EE_CS. Chip select line for the EEPROM
      15  (68800-6 +) DRAW_PIXEL_SIZE. Set to load drawing pixel size.
            If both bit 11 and 15 are 0 both pixel sizes are loaded
          (Mach8) EE_SELECT. Must be set to enable read/writing the EEPROM
Note: On the Mach32 this register can be read at 8EEEh

7EEEh W(R):  Bounds Accumulator Bottom Register                     (Mach8/32)
bit 0-15  BOUNDS_BOTTOM. The highest Y coordinate written through the linedraw
          register. Reset to -2048 when A2EEh bit 8 is set

7EEEh W(W):  ROM/EEPROM/DAC Control Register                          (Mach32)
bit    0  EE_DATA_OUT. Data output to the EEPROM
       1  EE_CLK. Clock signal for the EEPROM
       2  EE_CS. Chip select for EEPROM
       3  EE_SELECT. Enables the external EEPROM for reading and writing if
          set
     4-7  ROM_PAGE_SEL. Selects a 2K page within the 32K ROM
     8-9  BLANK_ADJUST. For type 2 DACs (ATI68875) only. Delays BLANK by 1 or
           2 PCLKs
   10-11  PIXEL_DELAY. Adjusts pixel data skew from PCLK
      12  PASSTHRU_OVERIDE. Allows the pixel clock to remain active even when
          PASSTHROUGH is 0
   13-15  CARD_SELECT. Allows selection of cards in multicard systems. The
          card is active if the card is strapped to this value or zero.

82EEh (R/W):  Pattern Data Index Register                           (Mach8/32)
bit  0-7  (68800-3) Selects 1 of 18 pattern data registers
     0-4  (68800-6 +) Selects one of 24 pattern data registers
Note: the data is written to 8EEEh. Each write increments this index
      Index 0-0Fh are the color pattern data registers, 10h-11h (10h-17h for
      the 68800-6 and later) are the mono pattern data registers.

8EEEh W(R):  Read Extended Graphics Engine Configuration Register     (Mach32)
bit  0-2  MONITOR_ALIAS. Alternate monitor ID for 8514/A application use
       3  ALIAS_ENA. If set read of the Subsystem Status register (42E8h)
          returns the monitor ID in bit 0-2 rather than the actual ID.
     4-5  PIXEL_WIDTH. Number of bits per pixel
              0: 4bits/pixel(bpp), 1: 8bpp, 2: 16bpp, 3: 24bpp
            16 and 24 bits per pixel only supported if we have at least 1MB
            and the DAC can handle it.
     6-7  16_BIT_COLOR_MODE. 16bit pixel format:
            0: (5,5,5) Red = bit 10-14, Green = bit  5-9, Blue = bit 0-4
            0: (5,6,5) Red = bit 11-15, Green = bit 5-10, Blue = bit 0-4
            0: (6,5,5) Red = bit 10-15, Green = bit  5-9, Blue = bit 0-4
            0: (6,6,4) Red = bit 10-15, Green = bit  4-9, Blue = bit 0-3
       8  MULTIPLEX_PIXELS. If set 4 pixels are sent to the DAC in parallel
       9  24_BIT_COLOR_CONFIG. If set 24bit pixel occupy 4 bytes and bit 10
          selects the unused byte within the pixel, if clear 24bit pixel occupy
           3 bytes.
      10  24_BIT_COLOR_ORDER. Selects the order the colors are stored in 24bit
          pixels. If set Red is stored first, if clear blue first.
             Bit10  Bit9    Red     Green    Blue
               0      0   Byte 2   Byte 1   Byte 0
               0      1   Byte 3   Byte 2   Byte 1
               1      0   Byte 0   Byte 1   Byte 2
               1      1   Byte 0   Byte 1   Byte 2
      11  (68800-6 +) DISPLAY_PIXEL_SIZE. Set to load display pixel size.
            If both bit 11 and 15 are 0 both pixel sizes are loaded
   12-13  DAC_EXT_ADDR. Connected to RS2 and RS3 on the DAC.
      14  DAC_8_BIT_EN. Set for 8bit DAC operation, clear for 6bit
      15  (68800-6 +) DRAW_PIXEL_SIZE. Set to load drawing pixel size.
            If both bit 11 and 15 are 0 both pixel sizes are loaded
Note: This register is written at 7AEEh

8EEEh W(W):  Color/Monochrome Pattern Data Registers                (Mach8/32)
bit 0-15  Pattern data. 82EEh selects the pattern data registers to write to.

92EEh W(R):  ROM Page Select & EEPROM Control Register                (Mach32)
bit  4-7  ROM_PAGE_SEL. Selects a 2K page within the 32K ROM
     8-9  BLANK_ADJUST. For type 2 DACs (ATI68875) only. Delays BLANK by 1 or
           2 PCLKs
   10-11  PIXEL_DELAY. Adjusts pixel data skew from PCLK

96EEh W(R/W):  Bresenham Count Register                             (Mach8/32)
bit 0-10  COUNT. The largest of the absolute values of delta X and delta Y

9AEEh W(R):  Extended FIFO Status Register                          (Mach8/32)
bit 0-15  Each bit is set if the corresponding FIFO location is occupied and
          clear if it is free. Bit 15 will clear first.

9AEEh (W):  Linedraw Index Register                                 (Mach8/32)
bit  0-2  Determines the type of line data written to FEEEh.
            0: Set current X, 1: Set current Y, 2: Line end X, 3: Line end Y,
            4: set current X, 5: Set current Y.
          Writing to FEEEh increments this index, except that 3 wraps to 2 and
          5 to 4 so that a polyline can be output by setting this index to 0
          and then writing the coordinates to FEEEh.