ati.txt

比较详尽的VGA端口寄存器的文档

bit  0-7  OVERSCAN_BLUE_24. Blue Overscan color for 16 and 24bit modes

3C0h index 00h-0Fh (R/W):  Palette index register
bit 4-5  Mode 67h Palette set selection. These bits should be the same in all
         16 attribute registers.
         Value   Pixel=0    1      2         3
          0       Black  White  Grey      Bright White
          1       Black  Green  Red       Yellow
          2       Black  Cyan   Red       White
          3       Black  Cyan   Magenta   White
Note: this is special to mode 67h only!!

3CEh index 50h (R/W):                                        (Mach32/64 only?)
bit  0-7  Lower 8 bits of the ATI extended register base I/O address

3CEh index 51h (R/W):                                        (Mach32/64 only?)
bit  0-3  Bits 8-11 of the ATI extended register base I/O address. Bits 0-7
          are in 3CEh index 50h.
     6-7  Selects the index range for the extended registers within the ATI
          extended registers. 0: 00h-3Fh, 1: 40h-7Fh, 2: 80h-BFh, 3: C0h-FFh
Note: Usually these registers are programmed to place the extended registers
      at 1CEh with index 80h-BFh. (50h = CEh and 51h = 81h).

6EEh (W):  24Bit Green Overscan Component                             (Mach32)
bit  0-7  OVERSCAN_GREEN_24. Green Overscan color for 16 and 24bit modes

6EFh (W):  24Bit Red Overscan Component                               (Mach32)
bit  0-7  OVERSCAN_RED_24. Red Overscan color for 16 and 24bit modes

0AEEh W(W):  Cursor Offset Low                                        (Mach32)
bit 0-15  CURSOR_OFFSET_LO. Lower bits of the address (in DWORDs) of the
          cursor map in video memory. The upper bits are in 0EEEh. The cursor
          map is a 64x64 pixel map with two bits per pixel.
          Pixel:    Pixel Color:
            0       Cursor Color 0
            1       Cursor Color 1
            2       Transparent (Screen data)
            3       Complement (XOR cursor)

0EEEh W(W):  Cursor Offset High                                       (Mach32)
bit  0-3  CURSOR_OFFSET_HI. Upper bits of the address of the cursor map. Low
          bits are in 0AEEh.
      15  CURSOR_ENA. Set to enable the Hardware Cursor

12EEh W(R):  Configuration Status 1 Register                           (Mach8)
bit    0  CLK_MODE. Set to use clock chip, clear to use crystals.
       1  BUS_16. Set for 16bit bus, clear for 8bit bus
       2  MC_BUS. Set for MicroChannel bus, clear for ISA/EISA bus
       3  EEPROM_ENA. EEPROM enabled if set
       4  DRAM_ENA. Set for DRAM, clear for VRAM.
     5-6  MEM_INSTALLED. Video memory. 0: 512K, 1: 1024K
       7  ROM_ENA. Set is ROM is enabled
       8  ROM_PAGE_ENA. Set if ROM paging enabled
    9-15  ROM_LOCATION. If bit 2 and 3 are 0 the ROM will be at this location:
           0: C000h, 1: C080h, 2: C100h, .. 127: FF80h (unlikely)

12EEh W(R):  Configuration Status 1 Register                          (Mach32)
bit    0  8514_ONLY. If set the VGA is disabled, if clear VGA and 8514 enabled
     1-3  BUS_TYPE. 0: ISA, 1:EISA, 2:16bit MCA, 3: 32bit MCA, 4: Local Bus
           (386SX), 5: Local Bus (386DX), 6: Local Bus (486), 7: PCI
     4-6  MEM_TYPE. Memory type:
            0: 256Kx4 DRAM
            1: 256Kx4 VRAM with 512bit serial transfer
            2: (68800-3) 256Kx4 VRAM with 256bit serial transfer
               (68800-6 +) 256Kx16 VRAM with 256bit serial transfer
            3: 256Kx16 DRAM
          Remaining only for 68800-6 and up:
            4: 256Kx4 Graphics DRAM
            5: 256Kx4 VRAM with 512bit split transfer
            6: 256Kx16 VRAM with 256bit spilt transfer
       7  CHIP_DIS. Chip disabled if set
       8  TST_VCTR_ENA. If set delay memory write data by 0.5 MCLK for test
          vector generation.
    9-11  DACTYPE: Indicates the type of RAMDAC installed:
            0: ATI 68830 (8bit i/f, 8 and 15/16bit modes)
            1: SC1148x, IMS-G173,MU9c4870 (8bit i/f, 8 and 15/16bit modes)
            2: ATI68875, Bt885, TLC34075 (24/32bit i/f, 8,15/16 and 24bit
                modes)
            3: Bt47x, INMOS17x (8bit i/f, 8bit modes - standard DAC)
            4: AT&T20c49x, Bt48x, IMS-G174, MU9c1880, MU9c4910, SC1502x
                 (8bit i/f, 8,15/16 and 24bit modes)
            5: ATI68860 (24/32/64bit i/f, 8,15/16 and 24bit modes)
               Only for 68800-AX
      12  MC_ADR_DECODE. Enable internal microchannel address decode if set,
          external if clear
   13-15  CARD_ID. Used for multiple controllers

12EE W(W):  Horizontal Cursor Position Register                       (Mach32)
bit 0-10  H_CUR_POSN. Cursor X-position in units of 8 pixels relative to the
          address in 2AEEh & 2EEEh

16EEh (R):  Configuration Status 2 Register                            (Mach8)
bit    0  SHARE_CLOCK. If set the Mach8 shares clock with the VGA
       1  HIRES_BOOT. Boot in hi-res mode if set
       2  EPROM_16_ENA. Adapter configured for 16bit ROM if set
       3  WRITE_PER_BIT. Write masked VRAM operations supported if set
       4  FLASH_ENA. Flash page writes supported if set

16EEh W(R):  Configuration Status 2 Register                          (Mach32)
bit    0  (68800-3 only) SLOW_SEQ_EN. Use 2 clock sequencer timing if set,
            1 clock sequencer timing if clear
       1  MEM_ADDR_DIS. Disable FE0000h-FFFFFFh if set
       2  ISA_16_ENA. (ISA bus only) 16bit ISA bus if set, 8bit if clear
       3  KOR_TXT_MODE_ENA. Korean character font support enabled if set
     4-5  LOCAL_BUS_SUPPORT.
            1: LOCAL2# local bus signal selected
            2: LOCAL3# local bus signal selected
            3: LOCAL1# local bus signal selected
       6  LOCAL_BUS_CONFIG_2. LBus_2 configuration (non-multiplexed) if set,
          LBus_1 configuration (multiplexed) if clear
       7  LOCAL_BUS_RD_DLY_ENA. If set read data is held for 1 bus clock after
          RDY
       8  LOCAL_DAC_EN. Disable local decode of RAMDAC write in local bus
          systems if set
       9  LOCAL_RDY_EN. Enable 1 bus clock RDY delay for write if clear
      10  EEPROM_ADR_SEL. Decode BIOS EEPROM at C0000h-C7FFFh if set, at
          E0000h-E7FFFh if clear
      11  GE_STRAP_SEL. (EISA bus) Enable POS register function if set, always
          enable chip if clear. (Local Bus) Enable local decode of 102h
          register if clear
      12  VESA_RDY. Enable VESA compliant RDY format if clear
      13  (68800-6 +) Z4GBYTE. Enable 4GN memory aperture if set, 128MB if
            clear
      14  (68800-6 +) LOC2_MDRAM. Supports 2MB DRAM in LBus_2 configuration if
            set, 1MB if clear

16EE W(W):  Vertical Cursor Position Register                         (Mach32)
bit 0-11  V_CUR_POSN. Cursor Y-position relative to the address in 2AEEh &
          2EEEh

1AEEh W(R):  FIFO Test Data Register                                  (Mach32)
bit 0-15  FIFO test data

1AEEh (W):  Cursor Color 0 Register                                   (Mach32)
bit  0-7  CUR_COLOR_0. Cursor Color 0. In 16 and 24 bit modes this is the Blue
          component of Cursor Color 0

1AEFh (W):  Cursor Color 1 Register                                   (Mach32)
bit  0-7  CUR_COLOR_1. Cursor Color 1. In 16 and 24 bit modes this is the Blue
          component of Cursor Color 1

1EEEh (W):  Horizontal Cursor Offset Register                         (Mach32)
bit  0-5  CUR_H_OFFSET. First horizontal pixel actually used within the 64x64
          cursor map.

1EEFh (W):  Vertical Cursor Offset Register                           (Mach32)
bit  0-5  CUR_V_OFFSET. Number of lines shown in the cursor

22EEh (R/W):  PCI Control Register                                  (68800-AX)
bit  0-2  DAC_RW_WS. RAMDAC read/write wait states
       3  TARGET_ABORT_EN. Enable Target Abort Cycle if set
       4  PCI_DAC_DLY. If set increases the hold time of the register select
          signals relative to the falling edge of the DAC write signal
       5  DAC_SNOOP_EN. Enables snooping on DAC read if set
       6  FAST_BURST. Enables 0 wait states on aperture Burst Write if set
       7  FAST_MEM_IO. Fast memory mapped I/O read/write enabled if set

26EEh (W):  CRT Pitch Register                                      (Mach8/32)
bit  0-7  Width of logical scanlines in units of 8 pixels.
          (Mach8) When 4AE8h or BEE8h index 5 is written this register is
            reset to 128 (=1024 pixels)

2AEEh W(W):  CRT Offset Low Register                                (Mach8/32)
bit 0-15  Lower 16 bits of the CRT Offset. The upper bits are in 2EEEh.
          The start of the displayed image in units of 4 bytes.

2EEEh W(W):  CRT Offset High Register                               (Mach8/32)
bit  0-3  Upper bits of the CRT Offset. Lower bits are in 2AEEh.

32EEh W(R/W):  Local Control Register                                 (Mach32)
bit    0  MED_NON-PAGE-CYC. Enables 6 clock non-page cycle
       1  LONG_NON-PAGE-CYC. Enables 7 clock non-page cycle
       2  SHORT_CAS_PULSE_EN. Enables 1/2 memory clock CAS precharge time
       3  DAC_BLANK_ADJ. Enables DAC to be clocked on positive clock edge
       4  FIFO_TEST. Enables testing of FIFO
     5-6  (68800-3) FIFO_TIMING_ADJ. Enables filtering of 1 clock IOW low or
            high pulse
       5  (68800-6 +) MEM_MAP_ENA. Enables Memory Mapped registers
             The memory mapped registers are located in the last 512 bytes of
             the aperture (1MB or 4MB). 4 bytes are allocated to each register
             Memory Address:  I/O register:
                 xFFE00         02E8h
                 xFFE04         06E8h
                   <Other xxE8h registers>
                 xFFEFC         FEE8h
                 xFFF00         02EEh
                 xFFF04         06EEh
                   <Other xxEEh registers>
                 xFFFFC         FEEEh
       6  (68800-6 +) LOC_BIOS_ENA. Enables Local Bus BIOS ROM Decode
     7-9  ROM_WAIT. Number of ROM wait states. Default is 7.
   10-11  MEM_R_DELAY. Additional wait states for memory reads. Default is 3
   12-15  (not 68800-AX on PCI bus) LOCAL_BUS_WAIT. Minimum wait states for
            local bus. Default is 15
          (68800-AX on PCI bus) 8514IO_WAIT. Number of wait states for I/O
            read/write operations.

36EEh (W):  FIFO Options Register                                      (Mach8)
bit    0  W_STATE_ENA. If clear wait states disabled unless FIFO is full, if
          set wait states are generated if the FIFO is at least half full.
          This bit does not affect wait states for 8514/A compatible registers
       1  HOST_8_ENA. Clear for 16bit I/O operations, set for 8bit I/O

36EEh W(R/W):  Miscellaneous Register                                 (Mach32)
bit    0  W_STATE_ENA. If clear wait states disabled unless FIFO is full, if
          set wait states are generated if the FIFO is at least half full.
          This bit does not affect wait states for 8514/A compatible registers
       1  HOST_8_ENA. Clear for 16bit I/O operations, set for 8bit I/O
     2-3  MEM_SIZE_ALIAS. Video Memory: 0: 512K, 1: 1MB, 2: 2MB, 3: 4MB
       4  DISABLE_VGA. VGA controller enabled if clear.
       5  16_BIT_IO. 16bit 8514 I/O enabled if set.
       6  DISABLE_DAC. Disables local DAC if set
       7  DLY_LATCH_ENA. For VRAM this is the serial data delay latch enable,
          for DRAM the memory data delay latch enable for bits 0-63.
       8  TEST_MODE. Extends draw engine page write cycle to 3 clocks for test
          purposes.
      10  (68800-6 +) BLK_WR_ENA. Block Write Enabled if set. Utilises the
            block write mode of most VRAMs which expands all '1' data bits to
            a specified color in the corresponding nibbles. '0 bits are no-ops
            Only supported if the memory type is 5 or 6.
      11  (68800-6 +) 64_DRAW_ENA. 64bit Draw Enable if set.
      12  MEM_DATA_SEL. If set video memory read data is latched on the rising
          edge of CASB, if clear it flows through.
      13  DLY_LATCH_ENA. Memory data delay latch enable for data bits 0-63
      14  LATCH_FULL_ENA. Memory Data Latch full clock pulse enable

3AEEh (R):  FIFO Test Tag Register                                    (Mach32)
bit  0-4  FIFO test data

3AEEh W(W):  Extended Cursor Color 0 Register                         (Mach32)
bit  0-7  EXT_CUR_COL_0_G. Green component of the Cursor Color 0 in 16 and
          24bit modes
    8-15  EXT_CUR_COL_0_R. Red component of the Cursor Color 0 in 16 and
          24bit modes

3EEEh W(W):  Extended Cursor Color 1 Register                         (Mach32)
bit  0-7  EXT_CUR_COL_1_G. Green component of the Cursor Color 1 in 16 and
          24bit modes
    8-15  EXT_CUR_COL_1_R. Red component of the Cursor Color 1 in 16 and
          24bit modes

42EEh (R/W):  Memory Boundary Register                                (Mach32)
bit  0-3  MEM_PAGE_BNDRY. Division between VGA and 8514 memory in 256K units.
           1: VGA can write in the first 256K, 8514 in all but the first 256K
           2: VGA can write in the first 512K, 8514 in all but the first 512K
           etc.
       4  MEM_BNDRY_ENA. If set the VGA and 8514 can only write in each their
          own memory area, if clear each can write in all of memory.

46EEh W(W):  Shadow Set Control Register                            (Mach8/32)
bit    0  LOCK_CRT_PARAMS. Locks the display mode CRT parameters - Double Scan
          and Interlace.
       1  LOCK_Y_CONTROL. Locks 22E8h bits 1-2