ati.txt

比较详尽的VGA端口寄存器的文档

       3  Write Protect Vertical Timing registers. If set write protects 3d4h
          index 6, 7 bits 0-3 and 5-7, 9 bit 5, 10h, 11h bits 0-3, 12h, 15h
          and 16h
       4  Write Protect CRT0A-CRT0B. If set write protects the Cursor Start
          and End registers (3d4h index 0Ah and 0Bh).
       5  Write Protect CRT08[0-6], CRT14[0-4]. If set write protects
          registers 3d4h index 8 bits 0-6 and index 14h bits 0-4
       6  Write Protect CRT00-CRT07. If set write protects 3d4h index 0-7
          except index 7 bit 4
       7  CRT11[7] Override. If set 3d4h index 11h bit 7 is ignored and does
          not lock other CRTC registers.

1CEh index B5h (R/W):  ATI Register 35 (ATI35)
bit    0  Blanking Signal Select. Select display enable as the blanking signal
          if set
       1  Blanking Polarity Invert. Inverts the polarity of the  blanking
          signal BLANKB if set
       2  Display Enable Signal Skewed. Skews the Display Enable signal by one
          PEL clock period if set
       3  Select Map 3 as programmable character generator
          (68800) General Purpose Read/Write bit.
       4  (18800-1 +) Enable 8 simultaneous fonts if set. Background is then
            always 0, and bit 4-7 of the attribute selects the font.
            The font location in plane 2 (sorted by attribute bit 4-7) is:
              0: 0K, 1: 32K, 2: 8K, 3: 40K, 4: 16K, 5: 48K, 6: 24K, 7: 56K
          (68800) Anti-alias Fonts Enable.
       5  Disable Cursor Blinking if set
       6  CGA Cursor Start/End Address. If set adds 5 to the cursor start and
          end registers for CGA emulation.
       7  Select undivided input clock as pixel clock
          (68800-6) VGA Overscan Output Enable. If set generates an overscan
            signal that can be used by the RAMDAC to select a color outside
            the normal 256color palette (overlay registers in the RAMDAC).

1CEh index B6h (R/W):  High Resolution Enable
bit    0  (28800-4 +) CRTC Display Address Counter Enable. Set to enable
            >16bit CRTC address counter. If clear the display wraps at 256K
            (planar modes - 4x64K) or 512K (packed modes - 8x64K).
       1  Enable 640x400 Hercules emulation if set
       2  Enable linear addressing in 256color modes if set
       3  Select 4 color high res modes
          (68800) General Read/Write bit.
       4  16 Color Enable, APA Mode. Set to enable 16 color high resolution
          modes. If set the horizontal timings (3d4h index 0-5) are doubled.
       5  Enable vertical interrupts if set
       6  (18800 - 28800-3) Enable linear addressing
          (?) Select composite sync for output
          (68800) Linear Addressing, Text Mode. Enables linear addressing in
            text modes if set.
       7  Screen Blanking Disable. Disable blanking screen blank in CGA and
          Hercules emulation if set

1CEh index B7h (R/W):  ATI Register 37 (ATI37)
bit    0  Status of ISA bus 16bit Operation Select.
          16bit if set, 8bit if clear
       1  (not 68800) PS/2 configuration
       2  (not 68800) Video memory is DRAM if set, VRAM if clear
       3  Output Data for the EEPROM input
       4  Status of ROM Address Decode. Decode enabled if set
       5  (not 68800) Select I/O address at 3xxh or 2xxh
     6-7  Reserved

1CEh index B8h (R/W):  Write Protect and Clock Select
bit    0  Write Protect ATTR00-0F. If set write protects the Palette registers
          (3C0h index 0-0Fh).
       1  Write Protect ATTR11. If set write protects the Overscan register
          (3C0h index 11h).
       2  Write Protect VGA Registers. If set write protects all VGA registers
          except the Display Start Address (3d4h index 0Ch,0Dh) and the Cursor
          Start and End registers (3d4h index 0Ah and 0Bh)
       3  Write Protect Register at I/O Port 3C2h if set
       4  (not 68800) Lock horizontal sync polarity if set
       5  (not 68800) Lock vertical sync polarity if set
          (68800) 640x300 Hercules Graphics Emulation. Enabled if set
     6-7  (Not 68800) Divide Video Clock by: 0: 1, 1: 2, 2: 3, 3: 4
       6  (68800) Clock Divider. If set divides the input Video Clock by 2.
       7  (68800) General Purpose Read/Write bit

1CEh index B9h (R/W):  ATI Register 39 (ATI39)
bit    0  (?) Clock select
       1  (18800-1 +) Select input to clock chip. See index BEh bit 4
          (68800) Documented as "General Purpose Read/Write bit", but is
            actually a Clock Select bit as for the earlier chips!
     2-3  ROM address space.
            0: 32k at C000h, 1: 28k at C000h, 2,3: 24k at C000h
     4-5  Wait cycles for 16 bit ROM access:
            0: 8 cycles, 1: 4 cycles, 2: 2 cycles, 3: none
          (68800) General Purpose Read/Write bits.
       6  16bit I/O Operation. If set I/O operations are 16bits, 8bits if
           clear
       7  Write Protect CRT18. If set write protects the Line Compare register
          (3d4h index 18h)

1CEh index BAh (R/W):  ATI Register 3A (ATI3A)
bit  0-2  (not 68800) Delay chain timing compensation for TTL monitors and
            16color RGB simulation
          (68800) General Purpose Read/Write bits
       3  (not 68800) Disable secondary Red output (for RGB monitors)
       4  (not 68800) Enable EGA color simulation for RGB monitors
       5  (not 68800) Enable monochrome grey scale circuit
       6  reserved
       7  (not 68800) Delay chain resolution compensation

1CEh index BBh (R/W):  Input Status Register
bit  0-3  Monitor Type:
            0: EGA
            1: PS/2 Analog Monochrome
            2: TTL Monochrome
            3: PS/2 Color
            4: RGB Color
            5: MultiSync
            7: PS/2 8514
            8: Seiko 1430
            9: NEC Multisync 2A
            A: Crystalscan 860/Tatung 1439
            B: NEC Multisync 3D
            C: TVM 3M
            D: NEC MultiSync XL
            E: TVM 2A
            F: TVM 3A
       4  (188xx) General read/write bit
          (28800 +) Bit 4 of the Monitor Type above
       5  (188xx) Video memory is 512Kbytes if set, 256K else
     6-7  Reserved
     0-7  (68800) General Purpose Read/Write bits
Note: this register is set by the BIOS

1CEh index BCh (R/W):  ATI Register 3C (ATI3C)
bit  0-7  reserved, must be 0

1CEh index BDh (R/W):  EGA Switch Settings
bit    0  Composite Sync Polarity Select.
       2  (28800-5 +) 128K CPU Address. Enables A0000h-BFFFFh as one 128K page
            if set
       3  Composite Sync Select. If set selects Composite Sync output, if
          clear Horizontal Sync.
     4-7  EGA switch settings

1CEh index BEh (R/W):  ATI Register E                              (not 18800)
bit    0  R/W Vertical Display End Register. If set unlock Vertical Display
          End register (3d4h index 12h) even in Double Scan modes.
       1  Interlace Operation. Set to enable interlace.
       2  Select Internal EGA DIP Switches. If set use 1CEh index BBh bits
          4-7, if clear use
       3  Read/Write Paging Select. Selects Read/Write bank mode if set,
          single bank mode if clear
       4  (18800-1 without 18810 Clock Chip (V4)) External clock select.
            Bit 2 of the clock select. Bits 0-1 are in 3C2h/3CCh bits 2-3.
            Clocks in MHz:
             0: 50.175, 1: 56.644, 3: 44.900, 4: 44.900, 5: 50.175, 7: 36.000
          (18800-1 with 18810 Clock Chip, 28800 +) Clock Select
              BEh bit 4: B9h bit 1: 3C2h bit 3: 3C2h bit 2:   Frequency:
                  0          0          0           0           42.954 MHz
                  0          0          0           1           48.771
                  0          0          1           0           Ext 0 (16.657)
                  0          0          1           1           36.000
                  0          1          0           0           50.350
                  0          1          0           1           56.640
                  0          1          1           0           Ext 1 (28.322)
                  0          1          1           1           44.900
                  1          0          0           0           30.240
                  1          0          0           1           32.000
                  1          0          1           0           37.500
                  1          0          1           1           39.000
                  1          1          0           0           40.000
                  1          1          0           1           56.644
                  1          1          1           0           75.000
                  1          1          1           1           65.000
          (68800) Documented as "General Purpose Read/Write bit", but is
            actually a Clock Select bit as for the earlier chips!
       6  (not 68800) Enable 1024x768 16 color mode
       7  (not 68800) Enable 1024x768 4 color mode

1CEh index BFh (R/W):  Miscellaneous Register                      (not 188xx)
bit    0  (68800) Disable Zero Wait State in planar modes if set
     1-3  (68800) Delay in number of MCLK cycles before latching first CPU
            data in 16bit planar modes.
       6  (288xx) ROM page address bit
       7  (288xx) Alternate memory organisation for graphics enable

23Ch (R):  Port A                                                 (18820 only)
bit  0-3  The data selected by 23Eh bits 5-6.
       5  Clear if the right mouse button is down.
       6  Clear if the middle mouse button is down.
       7  Clear if the left mouse button is down.
Note: The registers 23Ch-23Fh are relocated to 238h-23Bh if the secondary
      mouse port address is selected. This can be done in software or jumper.

23Ch (R/W):  Port A                                                    (288xx)
bit  0-2  Internal Register Index. Selects the register to access at 23Dh
       7  Set to reset the chip, clear for normal operation.
Note: The 28800 series has built in Inport Mouse support.
Note: The registers 23Ch-23Fh are relocated to 238h-23Bh if the secondary
      mouse port address is selected. This is done in software.

23Ch index 0 (R/W):  Mouse State                                       (288xx)
bit    0  Set if right mouse button is down
       1  Set if middle mouse button is down
       2  Set if left mouse button is down
       3  Set if the right mouse button state has changed since Hold was set
       4  Set if the middle mouse button state has changed since Hold was set
       5  Set if the left mouse button state has changed since Hold was set
       6  Set if the mouse has moved
       7  Set if packet complete
Note: this register is valid when 23Ch index 7 bit 5 is set

23Ch index 1 (R/W):  X Movement Count                                  (288xx)
bit  0-7  X-Count. Two's complement movement X count
Note: this register is valid when 23Ch index 7 bit 5 is set

23Ch index 2 (R/W):  Y Movement Count                                  (288xx)
bit  0-7  Y-Count. Two's complement movement Y count
Note: this register is valid when 23Ch index 7 bit 5 is set

23Ch index 7 (R/W):  Mode                                              (288xx)
bit  0-2  Timer Select. Sets the maximum interrupt rate. Interrupts only occur
          if the button state has changed or the mouse has moved.
           0: 0Hz (Never), 1: 30Hz, 2: 50Hz, 3: 100Hz, 4: 200Hz, 6: Always
       3  Data Interrupt Enable. If set an interrupt will be generated when
          the button state has changed or the mouse has moved.
       4  Timer Interrupt Enable. If set interrupts will be generated at the
          frequency specified in bits 0-2.
       5  Hold. Should be set before reading index 0-2 and reset after.
     6-7  Mode. 0: Quadrature Mouse.


23Dh (R/W):  Port B                                               (18820 only)
Note: only used to detect I/O address

23Eh (R/W):  Port C                                               (18820 only)
bit    0  (R) Set if IRQ5 selected
       1  (R) Set if IRQ4 selected
       2  (R) Set if IRQ3 selected
       3  (R) Set if IRQ2 selected
       4  Interrupts disabled if set, enabled if clear
     5-6  Counter Read Select. Selects the data to return in 23Ch bits 0-3
           0: Low nibble of X Counter
           1: High nibble of X Counter
           2: Low nibble of Y Counter
           3: High nibble of Y Counter
       7  Hold. Set this bit at the beginning of the Interrupt Service Rutine,
          clear after reading counter.

23Eh (R):  Port C                                                      (288xx)
Bit  0-7  Alternates between DEh and 11h on each read.

23Fh (R/W):  Port D                                               (18820 only)
bit  0-7  Used to control timer, must be 91h

2EEh (W):  Overscan Color Register                                    (Mach32)
bit  0-7  OVERSCAN_COLOR_8. Overscan color for 4 and 8bit modes

2EFh (W):  24Bit Blue Overscan Component                              (Mach32)