📄 weitek.txt
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Swapping of bits/bytes/halfword are controlled from a register.
The registers below are shown as M+xxxh, where M+xxxh is the Power9100 address
(even if the register does not exist for the Power9100). The corresponding
Power9000 address can be found as:
Power9100 Power9000
0000h - 1FFFh 100000h - 101FFFh
2000h - 3FFFh 180000h - 181FFFh
4000h - 7FFFh No match
The swap flags are added to the Power9000 address in bits 16-18 (see above).
3C4h index 12h (R/W):
bit 0-1 Base Address. 0: None, 1: A0000000h, 2: 20000000h, 3: 80000000h
2 Should be 0
3 Should be 1
4 P9000 Enabled if set, disable if clear
5 HSync polarity. Positive if clear, negative if set
6 VSync polarity. Positive if clear, negative if set
7 W5186 (or other VGA) Enabled if set, disabled if clear
3CDh (R/W): Bank Register: (Viper)
bit 0-5 Bank number. Maps a 64K block of the 4MB linear block at A000h, thus:
00h - 0Fh Maps 64K of the non-Power 9000 block
10h - 1Fh Maps a 64K Register block
20h - 3Fh Maps 64K of the Video memory
Note: This register only exists in the Viper (non-PCI versions) and is
implemented by external logic.
XXXXh (R/W): PCI Bank Register (Viper PCI)
bit 1-6 Bank number. Maps a 64K block of the 4MB linear block at A000h, thus:
00h - 0Fh Maps 64K of the non-Power 9000 block
10h - 1Fh Maps a 64K Register block
20h - 3Fh Maps 64K of the Video memory
Note: This register only exists in the Viper PCI systems and is (probably?)
implemented by external logic.
The Base address for this register is found from Offset 14h in the PCI
configuration space.
9100h (R/W): "PCI index register" (9100)
bit 0-7 Selects the offset into the 256byte PCI configuration space accessed
at 9104h. This allows access to the PCI configuration space even in
non-PCI systems.
9104h (R/W): "PCI data register" (9100)
bit 0-7 Each access to this register reads or writes the byte from the PCI
configuration space selected by 9100h. This allows access to the PCI
configuration space even in non-PCI systems.
M+0004h D(R/W): System Configuration Register
bit 0-2 Power 9000 version number. Always 0 on the 9100
9 Pixel writes go to buffer 1 if set, buffer 0 if clear
10 Pixel reads go to buffer 1 if set, buffer 0 if clear
11 If set swaps bits within each 32 bit DWORD when accessing display
memory (similar to the bit swap for register accesses)
12 If set swaps bytes within each 32 bit DWORD when accessing display
memory (similar to the byte swap for register accesses)
13 If set swaps halfwords within each 32 bit DWORD when accessing
display memory (similar to the halfword swap for register accesses)
14-22 The width of a scanline in pixels is determined by adding the
result of the three 3bit fields (Bits 14-16, 17-19 and 20-22).
Each field selects: 0: 0, 1: 32, 2: 64, 3: 128, 4: 256, 5: 512,
6: 1024, 7: 2048. Thus a width of 1280 is achieved by having
one field with 0, one with 4 and one with 6 (0+256+1024 = 1280).
23 Must be 0
24 If set the Frame Buffer Controller has double load, normal if clear
25 Must be 0
26-28 (9100) Pixel Size. 0: 8bpp, 1: 16bpp, 2: 24bpp
29-20 (9100) Shift3. Fourth subfield for the scanline width in bits 14-22
M+0008h D(R/W): Interrupt Register
bit 0 The drawing engine is idle if set, busy if clear
1 Must be set on writes for bit 0 to be updated. Reads as 1
2 If set a pick is done
3 Must be set on writes for bit 2 to be updated. Reads as 1
4 If set a vertical blanking has occured
5 Must be set on writes for bit 4 to be updated. Reads as 1
Note: The interrupt status bits (Bits 0,2,4) are sticky, once the condition
has occured they remain set until cleared by a write. If an interrupt
status bit (Bits 0,2,4) is set an interrupt will be generated if allowed
by the Interrupt Enable register (M+0000Ch).
M+000Ch D(R/W): Interrupt Enable
bit 0 If set allows interrupt when the drawing engine goes idle
1 Must be set on writes for bit 0 to be updated. Reads as 1
2 If set allows interrupt when a pick occurs
3 Must be set on writes for bit 2 to be updated. Reads as 1
4 If set allows interrupt when vertical blanking occurs
5 Must be set on writes for bit 4 to be updated. Reads as 1
6 If set allows interrupts as specified by bits 0,2 and 4, if clear
all interrupts are disabled
7 Must be set on writes for bit 6 to be updated. Reads as 1
M+0010h D(R/W): Alternate Read Bank (9100)
bit 16-22 Read bank. Selects the 64K block accessed by reading at Axxxxh
M+0014h D(R/W): Alternate Write Bank (9100)
bit 16-22 Write bank. Selects the 64K block accessed by writing to Axxxxh
M+0104h D(R): Horizontal Counter (hrzc)
bit 0-11 The currently displayed pixel in DDOTCLK clocks from the start of
Horizontal Retrace (Falling edge of HSYNC-).
M+0108h D(R/W): Horizontal Length (hrzt)
bit 0-11 The total number of DDOTCLK clocks in a scanline including blanking
. and retrace
M+010Ch D(R/W): Horizontal Sync Rising Edge (hrzsr)
bit 0-11 The HSYNC- pulse width in number of DDOTCLK clocks.
M+0110h D(R/W): Horizontal Blank Rising Edge (hrzbr)
bit 0-11 The number of DDOTCLK clocks from the start of horizontal retrace
(Falling edge of HSYNC-) to the end of blanking (Rising edge of
HBLNK-)
M+0114h D(R/W): Horizontal Blank Falling Edge (hrzbf)
bit 0-11 The number of DDOTCLK clocks from the start of the horizontal
retrace (Falling edge of HSYNC-) to the start of blanking (Falling
edge of HBLNK-)
M+0118h D(R/W): Horizontal Counter Preload Value (prehrzc)
bit 0-11 The value to load into the Horizontal Counter (M+100104h) when an
internal or external HSYNC- is received to allow synchronisation
with an external source. Should be set to 0 if external sync is not
used.
M+011Ch D(R): Vertical Counter (vrtc)
bit 0-11 The currently displayed line number
M+0120h D(R/W): Vertical Length (vrtt)
bit 0-11 The total number of lines in a frame including blanking and retrace
M+0124h D(R/W): Vertical Sync Rising Edge (vrtsr)
bit 0-11 The width of the Vertical Sync (VSYMC-) pulse in scanlines
M+0128h D(R/W): Vertical Blank Rising Edge (vrtbr)
bit 0-11 The number of scanlines from the start of Vertical Retrace (Falling
edge of VSYNC-) to the end of Vertical Blanking (Rising edge of
VBLNK-)
M+012Ch D(R/W): Vertical Blank Falling Edge (vrtbf)
bit 0-11 The number of scanlines from the start of Vertical Retrace (Falling
edge of VSYNC-) to the start of Vertical Blanking (Falling edge of
VBLNK-)
M+0130h D(R/W): Vertical Counter Preload Value (prevrtc)
bit 0-11 The value to load into the Vertical Counter (M+18011Ch) when an
internal or external VSYNC- is received to allow synchronization
with external video sources. Should be set to 0 if external sync is
not used.
M+0134h D(R): Screen Repaint Address (sraddr)
bit 0-11 The next VRAM row address to load into the VRAM. This is bits 10-21
of the linear memory address. When Vertical Blanking starts this
register is set to 0 (or the start address of the second buffer).
M+0138h D(R/W): Screen Repaint Timing Control (srtctl)
bit 0-2 QSF counter position. Selects which bit in the QSF counter register
(M+013Ch) causes the next row address transfer.
Typical values:
Memory 1 DDOTCLK 1 DDOTCLK
Config: = 4 dots = 8 dots
1 4 3
2 4 3
3 5 4
4 5 4
5 6 5
3 Set to select buffer 1 for display, clear to select buffer 0
4 Set to select Restricted (HBLNK- reload) mode, clear to select
normal (split shift) mode.
5 Set for normal operation, clear for Blanks asserted
6 Set to select Composite synchronization, clear to select separate
synchronization
7 Set to select internal HSYNC-, clear to select external HSYNC-
8 Set to select internal VSYNC-, clear to select external VSYNC-
M+013Ch D(R): QSF Counter (qsfcounter or sraddr_inc?)
bit 0-11 Counts DDOTCLK pulses within the current VRAM page, Ie. which bits
are shifted out of the VRAMs
Note: The sraddr_inc and qsfcounter register appears to be the same, but the
documentation leaves some doubt
M+0184h D(R/W): Memory Configuration (mem_config)
bit 0-2 Frame buffer VRAM configuration:
0: Memory Config 1. 8 256Kx4 VRAMs in 1 bank and 1 1Mpixel
buffer
1: Memory Config 2. 8 128Kx8 VRAMs in 2 interleaved banks and
1 1Mpixel buffer
2: Memory Config 3. 16 256Kx4 VRAMs in 2 interleaved banks and
1 2Mpixel buffer
3: Memory Config 4. 16 256Kx4 VRAMs in 2 interleaved banks and
2 1Mpixel buffers
4: Memory Config 5. 32 256Kx4 VRAMs in 4 interleaved banks and
2 2Mpixel buffers
M+0188h D(R/W): Refresh Period (rfperiod)
bit 0-9 The max time between memory refreshes in SYSCLK periods
M+018Ch D(R): Refresh Counter (rfcount)
bit 0-9 This register is decremented on each SYSCLK until it reaches 0,
when a refresh request is made and the register is reloaded from
the Refresh Period Register (M+0188h).
M+0190h D(R/W): RAS Low Maximum (rlmax)
bit 0-9 The maximum time the RAS- signal can be asserted in SYSCLK periods
M+0194h D(R): RAS low count (rlcur)
bit 0-9 When RAS- is asserted this register is loaded with the value in the
RAS Low Maximum register (M+0190h) and then decremented on each
SYSCLK until either RAS- is deasserted, or it reaches 0 in which
case a refresh sequence is started.
M+198h W(?): (9100)
bit 12-15 Number of FIFo slots free ??
Note: Apparently the IBM RGB525 DAC requires a read or write of this register
for the last write to a DAC register at 200h-23Ch takes effect ?
M+200h - M+23Ch D(R/W): DAC regs 0-15 (9100)
bit 0-7 Each access to one of these registers causes a read or write of
the corresponding DAC register (200h is REG00, 210h is REG04...)
The IBM RGB525 DAC apparently requires a read or write of M+198h
after a write to a DAC register ? Usually the same value is
repeated in all four bytes (bits 0-7, 8-15, 16-23 and 24-31) ?
M+2000h D(R): Status Register
bit 0 If set the source coordinates for a quad draw straddle the clipping
window
1 If set the source coordinates for a quad draw are entirely inside
the clipping window
2 If set the source coordinates for a quad draw are entirely outside
the clipping window
3 If set the requested quad is concave
4 If set an exception was encountered for a quad command, the
operation cannot be performed and must be done in software
5 If set an exception was encountered for a blit command, the
operation cannot be performed and must be done in software
6 If set an exception was encountered for a pixel command, the
operation cannot be performed and must be done in software
7 If set a pick was detected. (This is a copy of the pick bit in the
interrupt register (M+0008h bit 2)).
30 If set the drawing engine is busy
31 If set a Quad or Blit operation can not be started
M+2004h D(R): Blit command
Note: Reading this register issues a Blit command using X[0]/Y[0] as the upper
left corner of the source, X[1]/Y[1] as the lower right corner of the
source, X[2]/Y[2] as the upper left corner of the destination and
X[3]/Y[3] as the lower right corner of the destination. The source and
destination areas must be the same size. If the destination is out of
range bit 5 of the Status Register (M+2000h) is set and the operation
must be done in software.
Bit 31 of the Status Register (M+2000h) should be tested before a Quad
operation is issued.
M+2008h D(R): Quad command
Note: Reading this register issues a Quad command using X[0-3],Y[0-3] as
coordinates. If the Quad defined by the coordinates id concave or one
(or more) of the coordinates is out of range bit 4 of the Status
Register (M+2000h) is set and the operation must be done in software.
Bit 31 of the Status Register (M+2000h) should be tested before a Quad
operation is issued.
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