weitek.txt

比较详尽的VGA端口寄存器的文档

Weitek

  W5086
  W5186    1MB, BitBlt, Line draw
  W5286    As W5186 + Color expansion and fills

  Power9000    Max 2MB. Not VGA compatible, but VGA chip can be added.
               Accelerates 8bit operations.
  Power9001    PCI version of the Power9000
  Power9100    New version with a W5286 like VGA part built in. can handle
                8MB and accelerates 8/16/32bit operations



  Power9130    Video accelerator


W5x86 series:


3C0h index 15h (R/W):  Overscan Color High

3C4h (R/W):  Sequencer Index Register
bit  0-2  Sequencer index bits 0-2
       3  (W5086,W5186) Enable additional registers. If set enables registers
           at 300h, 301h, 30Ah, 320h and 32Ah
       4  Sequencer index high bit

3C4h index  5  (W):  Control Register 0
bit    2  SRS17. CRTC Display Start Address bit 16. Bits 0-15 are in 3d4h
          index 0Ch,0Dh
       6  BO. Bit Order. If clear bit 0 is displayed first (VGA)
       7  DVSAE. Dual Video Start Address/Offset Enable

3C4h index  6  (W):  Control Register 1
bit    3  BSE. Special Text Attributes. If set the text attributres are
          defined as follows:
          bit  0  Color 0 (Half bright in monochrome)
               1  Underline
               2  Reverse Video
               3  Blinking
               4  Bold
               5  Struck Through
               6  Color 1
               7  Color 2
       6  GHAE. Graphics Accelerator Enable. 0: Halt, 1: Enable

3C4h index 07h (R):  Revision Register
Bit  0-2  Revision Level.
     5-7  Chip ID. 1: W5186, 2: W5286 or P9100  (0: W5086 ???)

3C4h index 10h (R):  User Bits
bit  0-3  Manufacturer information. Read from straps at power-up.
     4-7  Always returns 9 for the W5186, 5 for the W5286 & P9100.

3C4h index 10h (W):  I/O Base
bit  0-7  Defines the upper 8 bits of the I/O base address. Default is 3 to
          map the registers at 3xxh

3C4h index 11h (R/W):  Miscellaneous
bit    5  Clear to enable extensions
       6  Clear to enable bank addressing
Note: to update this register, first it must be read and the value
      rewritten twice, then the changed value can be written

3C4h index 12h (R/W):  Output Control
bit  5-6  3 for 640x480, 1 for 800x600, 0 else
     6-7  (W5286) Memory. 0: 256K, 1: 512K, 2: 1MB
       7

3C4h index 13h (R/W):  Memory Base
bit  0-3  Base Memory address. Defines the location of the 1MB Linear Aperture
          in units of 1MB.

3CDh (R/W):  Bank Register
bit  0-3  Write Bank
     4-7  Read bank

3CEh (R/W):  Graphics Controller Index Register
bit  0-3  Index
       7  (R) Graphics Engine Busy if set

3CEh index 09h (R/W):  GHA Queue Base Address
bit  0-7  Base address of the Instruction Queue in units of 1KB (?). The
          Graphics engine uses a 4KByte Instruction Queue of 256 16byte
          instructions. Each instruction has this format:
          Byte  Bit  Description
           00h  0-3  Plane Mask. Each bit set enables writing in the
                     corresponding plane
                  4  Sync. If set the instruction is delayed until Vertical
                     Retrace occurs
                5-7  Opcode. 0: Short BitBLT, 1: Long BitBLT, 2: Short Screen
                     Move, 3: Long Screen Move, 4: Steep Line Draw, Flat Line
                     Draw, 6: Block Move, 7: NOP
           01h  0-7  Start Mask. Each bit set enables writing to the
                     corresponding bits in the first byte of each scanline
           02h 0-15  (BitBLT) Horizontal Total. The width of the blit area in
                      bytes (-1)
           02h 0-15  (Linedraw) Line Decrement. The amount to subtract from
                      the error term when moving parallel to the minor axis
           04h  0-3  Source Inversion Mask. Each bit if set causes source data
                     from the corresponding plane to be inverted before
                     applying the operation in Byte 05h (Color Plane Logical
                     Operation).
                4-7  Destination Inversion Mask. Each bit if set causes
                     destination data from the corresponding plane to be
                     inverted before applying the operation in Byte 05h (Color
                     Plane Logical Operation).
           05h  0-3  Color Plane Logical Operation 0 (LOP0)
                4-7  Color Plane Logical Operation 1 (LOP1)
                     The logical operation for each plane is controlled by one
                     bit from LOP0 and one from LOP1
                     LOP1  LOP0  Operation
                      0     0     Store (NOP)
                      0     1     AND
                      1     0     OR
                      1     1     XOR
           06h  0-7  End Mask. Each bit set enables writing to the
                     corresponding bits in the last byte of each scanline
           07h  0-7  Vertical Total. Height of the blit area in scanlines.
                     Bits 8-9 are in Byte 0Dh bits 6-7.
           08h 0-15  Destination Address. The offset from start of display
                     memory in bytes. Bits 16-17 are in Byte 0Dh bits 1-2
           0Ah 0-15  (BitBLT) Source Address. The offset from start of display
                      memory in bytes. Bits 16-17 are in Byte 0Fh bits 1-2.
           0Ah 0-15  (Linedraw) Line Initial Error. The Initial Error Term
           0Ch  0-7  Destination Pitch. The number of bytes in each scanline
                     at the destination. This is a 9bit two's complement value
                     (Bit 8 is in Byte 0Dh bit 0). Use a negative value if DIR
                     (Byte 0Fh bit 7) is set
           0Dh    0  Destination Pitch bit 8. Bits 0-7 are in Byte 0Ch
                1-2  Destination Address bits 16-17. Bits 0-15 are in Bytes
                      08h,09h
                3-5  Rotate Count. Number of bits to right-shift
                6-7  Vertical Total bits 8-9. Bits 0-7 are in Byte 07h
           0Eh  0-7  (BitBLT) Source Pitch. The number of bytes in each
                      scanline at the source. This is a 9bit two's complement
                      value (Bit 8 is in Byte 0Fh bit 0). Use a negative value
                      if DIR (Byte 0Fh bit 7) is set
           0Eh  0-7  (Linedraw) Line Increment. The amount to add to the
                      error term when moving parallel to the major axis
           0Fh  0-5  (Linedraw) Line Increment bits 8-13. Bits 0-7 are in Byte
                       0Eh
                  0  (BitBLT) Source Pitch bit 8. Bits 0-7 are in Byte 0Eh
                1-2  (BitBLT) Source Address bit 16-17. Bits 0-15 are in Byte
                       0Ah, 0Bh
                3-4  (BitBLT) Expansion Source. Selects the plane that holds
                      the source for the expansion.
                  5  (BitBLT) Expansion enable. If set color expansion is
                      enabled
                  6  Interrupt Disable. If clear an interrupt is generated
                     when the current instruction completes
                  7  Direction. If set the destination and source are
                     processed right-to-left and bottom-to-top

3CEh index 0Ah (R/W):  GHA Queue Tail Pointer
bit  0-7  Points to the entry in the Instruction Queue where we put the next
          instruction. First write the instruction to this position, then
          increment this register

3CEh index 0Bh (R/W):  GHA Queue Execution Pointer
bit  0-7  Points to the currently (or most recently) executing instruction in
          the Instruction Queue.

3CEh index 0Ch (W):  Extended Graphics
bit    2  Set in extended 256 color modes

3CEh index 0Dh (R/W):  GHA Bit Mask                                     (5286)
bit  0-7  Each bit enables updating the corresponding bit in each byte

3CEh index 0Eh W(R/W):  BCOLOR                                          (5286)
bit 0-15  Background color for color expansion.

3d4h index 19h (R/W):  Interlace

3d4h index 1Ah (R/W):  Serial Start Address High
bit  0-7  Bits 8-15 of the Start Address of the second frame buffer

3d4h index 1Bh (R/W):  Serial Start Address Low
bit  0-7  Bits 0-7 of the Start Address of the second frame buffer

3d4h index 1Ch (R/W):  Serial Offset
bit  0-7  CRTC Offset for the second frame buffer

3d4h index 1Dh (R/W):  Total Characters Per Line
bit  0-7  Number of character clocks displayed per line for the second frame
          buffer


ID Weitek VGA:

  old:=rdinx(SEQ,$11);
  outp(SEQ+1,old);
  outp(SEQ+1,old);
  outp(SEQ+1,inp(SEQ+1) or $20);
  if not testinx(SEQ,$12) then
  begin
    x:=rdinx(SEQ,$11);
    outp(SEQ+1,old);
    outp(SEQ+1,old);
    outp(SEQ+1,inp(SEQ+1) and $DF);
    if testinx(SEQ,$12) and tstrg($3CD,$FF) then
    begin
      _Weitek chip_
    end;
  end;
  wrinx(SEQ,$11,old);


Video Modes:

0054h  T   132   43
0055h  T   132   25
0056h  T   132   43  4color
0057h  T   132   25  4color
0058h  G   800  600   16c  PL4
0059h  G   800  600   16c  PL4
005Ah  G  1280 1024   16c  PL4
005Ch  G   800  600  256c  P8
005Dh  G  1024  768   16c  PL4
005Eh  G  1024  768  256c  P8
005Fh  G   640  480  256c  P8
0064h  T   132   60
0065h  T   132   50
0066h  T   132   60   4c
0067h  T   132   50   4c
0068h  T    80   60
0069h  G   640  480   16m  P24
006Ah  G   800  600   16c  PL4
006Ch  G   640  480  32Kc  P15
006Dh  G   800  600  32Kc  P15
006Eh  G   640  480  64Kc  P16
006Fh  G   800  600  64Kc  P16



Power 9000/9100:
The Power 9000 and 9100 have different memory and register layouts.
Also the different brands of Power9000/9100 boards all have different
Linear Aperture addresses, DAC access and special registers

The registers and video memory of the Power 9000 are mapped in a 4MB linear
memory block staring at M (typically 20000000h, 80000000h or A0000000h):

M+000000h - M+0FFFFFh  (1MB) Non-Power 9000 use
M+100000h - M+1FFFFFh  (1MB) Registers. The registers are 32bit and internally
                             stored in Big Endian format. Bits 16-18 of the
                             address are used to access the register with
                             different combinations of bit, byte and halfword
                             (16bit) swaps:
                              +00000h
                              +10000h  Swap bits
                              +20000h  Swap bytes
                              +30000h  Swap bytes and bits
                              +40000h  Swap Halfwords
                              +50000h  Swap Halfwords and bits
                              +60000h  Swap Halfwords and bytes
                              +70000h  Swap Halfwords, bytes and bits
                             Bits 13-15 of the address appears to be ignored.
M+200000h - M+3FFFFFh  (2MB) Video memory

The Power9100 has a more compact register layout where the registers are in
one 32Kbyte block, accessible either at A000h or in the Linear Aperture.