xga.txt

比较详尽的VGA端口寄存器的文档

21xAh index 1Eh  (W): Horizontal Sync Position 2.
bit   1-2  SYNC_PULSE_DLY2. Can delay the sync pulses half a character clock
             0 = no change, 2 = delay sync 4 pixels.
Note: This register should be programmed with the same value as index 1Ch.

21xAh index 20h  W(R/W): Vertical Total.
bit  0-10  Total number of scanlines (-1) in a frame.

21xAh index 22h  W(R/W): Vertical Displayed End.
bit  0-10  Number of displayed scanlines (-1).

21xAh index 24h  W(R/W): Vertical Blanking Start.
bit  0-10  The scanline relative to the start of display where the Vertical
           Blanking Starts.

21xAh index 26h  W(R/W): Vertical Blanking End.
bit  0-10  The scanline relative to the start of display where the Vertical
           Blanking Ends.

21xAh index 28h  W(R/W): Vertical Sync Start.
bit  0-10  The scanline relative to the start of display where the Vertical
           Sync Starts.

21xAh index 2Ah  (R/W): Vertical Sync End.
bit   0-7  The scanline relative to the start of display where the Vertical
           Sync Ends.

21xAh index 2Ch  W(R/W): Vertical Line Compare.
bit  0-10  The scanline relative to the start of display where the display
           wraps to line 0.

21xAh index 30h  W(R/W):  Sprite Position X
bit  0-10  The X position of the Sprite Hotspot in pixels.

21xAh index 32h  (R/W):  Sprite Hotspot X
bit   0-5  The X hotspot position of the sprite from the left.

21xAh index 33h  W(R/W):  Sprite Position Y
bit  0-10  The Y position of the Sprite Hotspot in pixels.

21xAh index 35h  (R/W):  Sprite Hotspot Y
bit   0-5  The Y hotspot position of the sprite from the top.

21xAh index 36h  (R/W): Sprite Control.
bit     0  If set the sprite is displayed on the screen.
Note: Sprite display must be disabled when modifying the sprite data.

21xAh index 38h  (R/W): Sprite Color 0 Red
bit   0-7  The red level of sprite color 0.
Note: In the original XGA bits 0-1 are ignored.

21xAh index 39h  (R/W): Sprite Color 0 Green
bit   0-7  The green level of sprite color 0.
Note: In the original XGA bits 0-1 are ignored.

21xAh index 3Ah  (R/W): Sprite Color 0 Blue
bit   0-7  The blue level of sprite color 0.
Note: In the original XGA bits 0-1 are ignored.

21xAh index 3Bh  (R/W): Sprite Color 1 Red
bit   0-7  The red level of sprite color 0.
Note: In the original XGA bits 0-1 are ignored.

21xAh index 3Ch  (R/W): Sprite Color 1 Green
bit   0-7  The green level of sprite color 0.
Note: In the original XGA bits 0-1 are ignored.

21xAh index 3Dh  (R/W): Sprite Color 1 Blue
bit   0-7  The blue level of sprite color 0.
Note: In the original XGA bits 0-1 are ignored.

21xAh index 40h  24(R/W): Start Address.
bit  0-18  The start display address in units of 8 bytes.

21xAh index 43h  W(R/W): Pixel Map Width.
bit  0-10  Length of scanline in units of 8 bytes.

21xAh index 50h  (R/W): Display Control 1.
bit   0-1  BLANK_DISP. 0 = display blanked, CRTC reset.
                       1 = display blanked, preparing CRTC reset
                       3 = Normal operation.
        3  INTERLACED. If set the display is interlaced.
        4  FEATURE_ENAB. If set the feature connector is enabled.
           usually enabled in VGA modes and disabled in 132 column text
           modes and extended XGA modes.
      6-7  SYNC_POLAR. Sync polarity (6=Vertical, 7=Horizontal).
               0=768 lines, 1=400 lines, 2=350 lines, 3=480 lines
Note: on writes bit 2 must be set to 1 and bit 5 must be preserved.

21xAh index 51h  (R/W): Display Control 2.
bit   0-2  DSPPIX_SIZE. Bits per pixel (for the CRT controller):
               0=1 bpp, 1=2 bpp, 2=4 bpp, 3=8 bpp, 4=16 bpp
               5 might be used for 24 bit on some clones.
      4-5  HSCALE. Horizontal pixel replication:
               0=Normal, 1=each pixel is doubled, 2=each pixel is quadrupled??
      6-7  VSCALE. Vertical pixel replication:
               0=Normal, 1=each line is doubled, 2=each line is quadrupled??

21xAh index 52h  (R): Monitor ID and Gun Output
bit   0-3  MONITOR_ID. Monitor types sensed from the monitor outputs:
               9   IBM 8507/IBM 8604   Mono 1024x768
              0Ah  IBM 8514            Color 1024x768
              0Bh  IBM 8515            Color 1024x768
              0Dh  IBM 8503            Mono 640x480
              0Eh  IBM 8512/IBM 8513   Color 640x480
              0Fh  No monitor attached
        5  RED_OUT.   Current output of the red gun. 1=high, 0=low.
        6  GREEN_OUT. Current output of the green gun. 1=high, 0=low.
        7  BLUE_OUT.  Current output of the blue gun. 1=high, 0=low.

21xAh index 54h  (R/W): Clock Select 1.
bit   0-1  CLK_SCALE. Divide factor for the clock:
               0=no divide, 1=divide by 2
      2-3  CLK_SEL1. Selects the video clock for the display:
              0 = VGA 8-pixel text mode & 640x480 graphics
                  If the CLK_SEL2 bit of the CLOCK_SEL2 register
                  (21xAh index 70h) is set this is 132 column text mode.
              1 = VGA 9-pixel text mode.
              2 = Clock from the feature connector
              3 = 1024x768 interlaced graphics
        7  (XGA-NI only)  PROG_CLK_SEL. If set and CLK_SEL1 and CLK_SEL2 are
           cleared, the PLL is selected as the clock source for the display.
           This bit should be cleared if CLK_SEL1 or CLK_SEL2 are non-zero.

21xAh index 55h  (R/W): Border Color.
bit   0-7  Palette index of the border or overscan color.

21xAh index 58h  (R/W):  PLL Program Register                    (XGA-NI only)
bit   0-5  The value for the PLL.
           Value = (Desired frequency * Factor from FREQ_SCALE) - 65
      6-7  FREQ_SCALE. Divisor for the frequency:
              0 = Divide by 4. Allowing 16.25 - 32.00MHz in 0.25MHz steps
              1 = Divide by 2. Allowing 32.50 - 64.00MHz in 0.50MHz steps
              2 = No divide, allowing 65.00 - 128.00MHz in 1MHz steps
Note: The XGA-NI should not be programmed for more than 90MHz.

21xAh index 59h  (R/W):  Direct Color Control                    (XGA-NI only)
bit   0-2  DC_MODIF. This field controls how the missing red and blue bits
           are handled in 64k color mode.
              0 = Zero Intensity Black mode.  Set to 0.
              1 = Non-Zero Color mode. Set to 1 unless color is 0.
              2 = same as 0.
              3 = Full Intensity White mode.  Set to 1.
              4 = Linearized Color mode.
                  Set to most significant bit of same color (bit 4).

21xAh index 60h  W(R/W): Sprite/Palette Address Index.
bit  0-13  Index for the Palette (8 bits) and Sprite (14 bits).
           For sprite accesses the index will increment after each
           byte access, for palette access the index will increment
           after each 3 or 4 byte pixel.

21xAh index 62h  (R/W): Sprite/Palette Index with Prefetch.
bit  0-13  Index for the Palette (8 bit) or Sprite (14 bit).
           When this register is written the Palette & Sprite Prefetch
           registers (index 67h-69h and 6Bh) are loaded with the appropriate
           data from the Palette and Sprite and the index.

21xAh index 64h  (R/W): Palette Mask
bit   0-7  Each display byte is anded with this value before reaching the DAC.
           Usually set to 0FFh.

21xAh index 65h  (R/W): Palette Data Port.
bit  0-7  Palette data is read and written to this port.
          Each read or write of the register will increment the
          palette address, first through the Red, Green Blue
          cycle, and then increment the Palette Address Index.

21xAh index 66h  (R/W): Palette Sequence
bit   0-1  COLOR_COMPNT. Shows the next palette entry access:
              0=Red, 1=Green, 2=Blue, 3="extra"
        2  COLOR_FORMAT. If set the palette is organised as (Red, Blue, Green
           and extra), if clear the format is (Red, Green and Blue).
           The 4 byte format allows reading a full palette entry in one double
           word access from index 67h-69h

21xAh index 67h  (R/W):  Palette Red Prefetch
bit   0-7  When the Palette Prefetch index (index 62h) is written this
           register is loaded with the red component.

21xAh index 68h  (R/W):  Palette Blue Prefetch
bit   0-7  When the Palette Prefetch index (index 62h) is written this
           register is loaded with the blue component.

21xAh index 69h  (R/W):  Palette Green Prefetch
bit   0-7  When the Palette Prefetch index (index 62h) is written this
           register is loaded with the green component.

21xAh index 6Ah  (R/W):  Sprite Data
bit   0-7  Sprite data is read and written through this register, incrementing
           the Sprite Index (index 60h). Each byte contains 4 2bit pixels
           with the following values:
              0=Sprite Color 0, 1=Sprite Color 1, 2=transparent, 3=Invert

21xAh index 6Bh  (R/W):  Sprite Data Prefetch
bit   0-7  This register is loaded with sprite data when the Sprite Prefetch
           Index (index 62h) is written.

21xAh index 6Ch  (R/W):  Miscellaneous Control                   (XGA-NI only)
bit     0  BLNK_REDBLUE. If set the red and blue outputs of the DAC are set
           to 0.

21xAh index 6Dh  (R/W):  MFI Control                             (XGA-NI only)
bit     0  MFI_ENABLE. If set the remaining bits in this register are valid
           and textmode attributes are interpreted as MFI attributes:
            bit 0-3  Foreground color (same as VGA text mode)
                  4  If set the first and last pixel in the underline scanline
                     is set (unless the character is underlined, in which case
                     they are clear).
                  5  If set the character is underlined.
                  6  If set the character is reversed
                  7  If VGA character blink is enabled, this bit controls
                     blinking, if not it sets the background color to 8.
                     MFI blinking uses a 75% on/25% off-cycle as opposed
                     to the VGA 50% blink cycle.
        1  CURSOR_TYPE. If set the cursor reverses the ForeGround and
           background, if clear it uses the ForeGround color.
        2  CURS_BLINK_DISAB. If set the cursor will not blink, if clear the
           cursor blinks at 1/32 the vertical refresh.
        3  CONST_COLOR_CURS. If set the cursor is the color in CURS_COLOR,
           if clear the cursor is the ForeGround color.
      4-7  CURS_COLOR. Color of the cursor in IRGB format if CONST_COLOR_CURS
           and NFI_ENABLE are set.

21xAh index 70h  (R/W):  Clock Select 2
bit     7  CLK_SEL2. Set in 132 column text mode, clear in other modes.

21xAh index 72h-73h.  RESERVED for VESA extensions.

21xAh index 74h  (R):  DMA Channel Readback.             (VESA - ISA bus only)
bit     0  DMA Channel Enable.  Indicates whether the DMA channel is enabled
           for bus-mastering.
      1-3  DMA Channel Select. Selects the DMA channel for bus master
           arbitration.
             0 = Channel 0, 1 = Channel 1, 2 = Channel 2, 3 = Channel 3,
             5 = Channel 5, 6 = Channel 6, 7 = Channel 7

21xAh index 75h  (?):  Subsystem Vendor ID.                             (VESA)
bit   0-7  After setting the index (port 21xAh) the first byte read from 21xBh
           is one of three values:
                00h  The subsystem vendor ID mechanism is not implemented.
            01h-FEh  Chip manufactor assigned subsystem vendor ID.