testbench.vhd

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

                END IF;
                bus_cycle(bus_cmd => bus_write,
                         byte    => command.byte,
                         data    => 16#98#,
                         dataHi  => 0,
                         sector  => 0,
                         Address => Addr);

                bus_cycle(bus_cmd => bus_standby,
                         byte    => command.byte);



            WHEN w_suspend =>
                bus_cycle(bus_cmd => bus_write,
                         byte    => command.byte,
                         data    => 16#B0#,
                         dataHi  => 0,
                         sector  => -1);

                bus_cycle(bus_cmd => bus_standby,
                         byte    => command.byte);

            WHEN w_resume =>
                bus_cycle(bus_cmd => bus_write,
                         byte    => command.byte,
                         data    => 16#30#,
                         dataHi  => 0,
                         sector  => -1);

                bus_cycle(bus_cmd => bus_standby,
                         byte    => command.byte);


            WHEN w_data =>

                D_hi :=  command.d_hi MOD 16#100#;
                D_lo :=  command.d_lo ;
                Addr :=  command.addr;
                Sect :=  command.sect;

                bus_cycle(bus_cmd => bus_write,
                         byte     => command.byte,
                         data     => D_lo,
                         dataHi   => D_hi,
                         sector   => Sect,
                         address  => Addr);

                bus_cycle(bus_cmd => bus_standby,
                         byte    => command.byte);


                IF NOT command.byte THEN
                    Addr := Addr*2;
                END IF;

                --write value(s) in default mem
                IF status = erase_active AND Sec_Prot(Sect)/='1'THEN
                    --sector should be erased
                    mem(Sect) := (OTHERS=>16#FF#);

                ELSIF status = erase_na AND Sec_Prot(Sect)/='1'THEN
                    --sector erase terminated = data integrity violated
                    mem(Sect) := (OTHERS=>-1);

                ELSIF status = readX AND Sec_Prot(Sect)/='1' THEN
                    mem(Sect)(Addr) := -1;
                    IF NOT command.byte THEN
                        mem(Sect)(Addr+1) := -1;
                    END IF;

                -- Write to Secure Silicon Sector Region
                ELSIF status = rd_SecSi AND FactoryProt/='1' THEN
                    slv_1 := to_slv(d_lo,8);
                    IF SecSi(Addr)>-1 THEN
                        slv_2 := to_slv(SecSi(Addr),8);
                    ELSE
                        slv_2 := (OTHERS=>'X');
                    END IF;

                    FOR i IN 0 to 7 LOOP
                        IF slv_2(i)='0' THEN
                            slv_1(i):='0';
                        END IF;
                    END LOOP;
                    SecSi(Addr) := to_nat(slv_1);
                    IF NOT command.byte THEN
                        slv_1 := to_slv(d_hi,8);
                        IF SecSi(Addr+1)>-1 THEN
                            slv_2 := to_slv(SecSi(Addr+1),8);
                        ELSE
                            slv_2 := (OTHERS=>'X');
                        END IF;
                        FOR i IN 0 to 7 LOOP
                            IF slv_2(i)='0' THEN
                                slv_1(i):='0';
                            END IF;
                        END LOOP;
                        SecSi(Addr+1) := to_nat(slv_1);
                    END IF;

                ELSIF status=buff_wr_busy THEN
                    --Write to Buffer command cycle
                    null;

                ELSIF status=erase_na THEN
                    --sector erase command sequence violation
                    null;

                -- Write to Flash Memory Array
                ELSIF status /= err AND Sec_Prot(Sect)/='1'THEN
                    slv_1 := to_slv(d_lo,8);
                    IF mem(Sect)(Addr)>-1 THEN
                        slv_2 := to_slv(mem(Sect)(Addr),8);
                    ELSE
                        slv_2 := (OTHERS=>'X');
                    END IF;

                    FOR i IN 0 to 7 LOOP
                        IF slv_2(i)='0' THEN
                            slv_1(i):='0';
                        END IF;
                    END LOOP;
                    mem(Sect)(Addr) := to_nat(slv_1);
                    IF NOT command.byte THEN
                        slv_1 := to_slv(d_hi,8);
                        IF mem(Sect)(Addr+1)>-1 THEN
                            slv_2 := to_slv(mem(Sect)(Addr+1),8);
                        ELSE
                            slv_2 := (OTHERS=>'X');
                        END IF;
                        FOR i IN 0 to 7 LOOP
                            IF slv_2(i)='0' THEN
                                slv_1(i):='0';
                            END IF;
                        END LOOP;
                        mem(Sect)(Addr+1) := to_nat(slv_1);
                    END IF;
                END IF;


            WHEN    wt          =>
                WAIT FOR command.wtime;

            WHEN    wt_rdy      =>
                IF T_RY/='1' THEN
                    WAIT UNTIL rising_edge(T_RY) FOR command.wtime;
                END IF;

            WHEN    wt_bsy      =>
                IF T_RY='1' THEN
                    WAIT UNTIL falling_edge(T_RY) FOR command.wtime;
                END IF;

            WHEN    OTHERS  =>  null;
        END CASE;
    END PROCEDURE;


    VARIABLE cmd_cnt    :   NATURAL;
    VARIABLE command    :   cmd_rec;  --

BEGIN
    Pick_TC (Model   =>  "AM29LV640MH90R"   );

    Tseries <=  ts_cnt  ;
    Tcase   <=  tc_cnt  ;

    Generate_TC
        (Model       => "AM29LV640MH90R"  ,
         Series      => ts_cnt,
         TestCase    => tc_cnt,
         command_seq => cmd_seq);


    cmd_cnt := 1;
    WHILE cmd_seq(cmd_cnt).cmd/=done LOOP
        command:= cmd_seq(cmd_cnt);
        IF command.sect = -1 THEN
            command.sect := ProtSecNum;
        END IF;
        status   <=  command.status;
        sts_check<=  to_slv(command.d_lo,8); --used only for toggle/status check
        cmd_dc(command);
        cmd_cnt :=cmd_cnt +1;

    END LOOP;

END PROCESS tb;

--process to monitor WP#
PROCESS(T_WPNeg)
VARIABLE reg : std_logic;
BEGIN
    IF falling_edge(T_WPNeg) THEN
        reg := Sec_Prot(ProtSecNum);
        Sec_Prot(ProtSecNum) := '1';
    ELSIF rising_edge(T_WPNeg) THEN
        Sec_Prot(ProtSecNum) := reg;
    END IF;
END PROCESS;

--------------------------------------------------------------------------------
-- Checker process,
-- Bus transition extractor: when bus cycle is read samples addr and data
-- Transition checker      : verifies correct read data using default memory
--------------------------------------------------------------------------------
checker: PROCESS
    VARIABLE RAddr      :   NATURAL;
    VARIABLE RSect      :   NATURAL;
    VARIABLE longread   :   boolean;
    VARIABLE shortread  :   boolean;
    VARIABLE toggle     :   boolean:=false;
    VARIABLE toggle_sts :   std_logic_vector(7 downto 0);

BEGIN
--    Transition extractor
    IF (T_CENeg='0'AND T_OENeg='0'AND T_WENeg='1') THEN
        IF T_BYTENeg='1' THEN
            RAddr := to_nat(T_A(14 downto 0)&'0');
        ELSE
            RAddr := to_nat(T_A(14 downto 0)&T_DQ(15));
        END IF;
        RSect := to_nat(T_A(HiAddrBit downto 15));

        shortread:= false;
        longread := false;

        --DUT specific timing
        IF (T_CENeg'EVENT OR T_WENeg'EVENT OR T_A(HiAddrBit downto 2)'EVENT)AND   --
           (status=read OR status=rd_cfi OR status=rd_secsi) THEN --OR status=readX)
            longread := true;
            CASE TimingModel IS
                WHEN    "AM29LV640MH90R"    |
                        "AM29LV640ML90R"   =>  WAIT FOR 95 ns;
--                WHEN  "AM29LV640MH101"  |
--                        "AM29LV640ML101"   =>  WAIT FOR 105 ns;
--                WHEN  "AM29LV640MH101R" |
--                        "AM29LV640ML101R"  =>  WAIT FOR 105 ns;
--                WHEN  "AM29LV640MH112"  |
--                      "AM29LV640ML112"   =>  WAIT FOR 115 ns;
--                WHEN  "AM29LV640MH112R" |
--                      "AM29LV640ML112R"  =>  WAIT FOR 115 ns;
--                WHEN  "AM29LV640MH120"  |
--                      "AM29LV640ML120"   =>  WAIT FOR 125 ns;
--                WHEN  "AM29LV640MH120R" |
--                      "AM29LV640ML120R"  =>  WAIT FOR 125 ns;
                WHEN OTHERS                 =>
                    REPORT "Timing model NOT supported : "&TimingModel
                    SEVERITY error;
            END CASE;

        ELSIF T_A(1 downto 0)'EVENT OR
             (T_DQ(15)'EVENT AND T_BYTENeg='0')OR
             (T_BYTENeg'EVENT) OR
              T_OENeg'EVENT OR
              (status/=read AND status/=rd_cfi AND
               status/=rd_secsi)  THEN  --AND status/=readX)
            shortread:=true;
            CASE TimingModel IS
                WHEN    "AM29LV640MH90R"    |
                 "AM29LV640ML90R"   =>  WAIT FOR 30 ns;
--                WHEN  "AM29LV640MH101"  |
--                        "AM29LV640ML101"   =>  WAIT FOR 40 ns;
--                WHEN  "AM29LV640MH101R" |
--                        "AM29LV640ML101R"  =>  WAIT FOR 40 ns;
--                WHEN  "AM29LV640MH112"  |
--                        "AM29LV640ML112"   =>  WAIT FOR 45 ns;
--                WHEN  "AM29LV640MH112R" |
--                        "AM29LV640ML112R"  =>  WAIT FOR 45 ns;
--                WHEN  "AM29LV640MH120"  |
--                       "AM29LV640ML120"   =>  WAIT FOR 45 ns;
--                WHEN  "AM29LV640MH120R" |
--                      "AM29LV640ML120R"  =>  WAIT FOR 45 ns;
                WHEN OTHERS                 =>
                    REPORT "Timing model NOT supported : "&TimingModel
                    SEVERITY error;
            END CASE;

        END IF;



        --Checker
        IF longread OR shortread THEN

            CASE status IS
                WHEN none       =>
                    toggle := false;

                -- read memory array data
                WHEN read       =>
                    toggle := false;
                    Check_read (
                        DQ       => T_DQ,
                        D_lo     => mem(RSect)(RAddr),
                        D_hi     => mem(RSect)(RAddr+1),
                        Byte     => T_BYTENeg,
                        check_err=> check_err);

                -- read secure silicon region
                WHEN rd_secsi =>
                    toggle := false;
                    Check_SecSi (
                        DQ       => T_DQ,
                        D_lo     => SecSi(RAddr),
                        D_hi     => SecSi(RAddr+1),
                        Byte     => T_BYTENeg,
                        check_err=>check_err);


                --read CFI query codes
                WHEN rd_cfi =>
                    RAddr := to_nat(T_A(14 downto 0));   --x16 addressing
                    toggle := false;
                    Check_CFI (
                        DQ       => T_DQ,
                        D_lo     => CFI_array(RAddr) ,
                        D_hi     => 0 ,
                        Byte     => T_BYTENeg,
                        check_err=>check_err);