testbench.vhd

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

    SHARED VARIABLE tc_cnt  :   NATURAL RANGE 0 TO 10:=0;    -- testcase counter


    BEGIN
        DUT : my_mem
        GENERIC MAP (
            -- tipd delays: interconnect path delays
            tipd_A0             => VitalZeroDelay01, --
            tipd_A1             => VitalZeroDelay01, --
            tipd_A2             => VitalZeroDelay01, --
            tipd_A3             => VitalZeroDelay01, --
            tipd_A4             => VitalZeroDelay01, --
            tipd_A5             => VitalZeroDelay01, --
            tipd_A6             => VitalZeroDelay01, --
            tipd_A7             => VitalZeroDelay01, --
            tipd_A8             => VitalZeroDelay01, --
            tipd_A9             => VitalZeroDelay01, --address
            tipd_A10            => VitalZeroDelay01, --lines
            tipd_A11            => VitalZeroDelay01, --
            tipd_A12            => VitalZeroDelay01, --
            tipd_A13            => VitalZeroDelay01, --
            tipd_A14            => VitalZeroDelay01, --
            tipd_A15            => VitalZeroDelay01, --
            tipd_A16            => VitalZeroDelay01, --
            tipd_A17            => VitalZeroDelay01, --
            tipd_A18            => VitalZeroDelay01, --
            tipd_A19            => VitalZeroDelay01, --
            tipd_A20            => VitalZeroDelay01, --
            tipd_A21            => VitalZeroDelay01, --

            tipd_DQ0            => VitalZeroDelay01, --
            tipd_DQ1            => VitalZeroDelay01, --
            tipd_DQ2            => VitalZeroDelay01, --
            tipd_DQ3            => VitalZeroDelay01, --
            tipd_DQ4            => VitalZeroDelay01, --
            tipd_DQ5            => VitalZeroDelay01, --
            tipd_DQ6            => VitalZeroDelay01, -- data
            tipd_DQ7            => VitalZeroDelay01, -- lines
            tipd_DQ8            => VitalZeroDelay01, --
            tipd_DQ9            => VitalZeroDelay01, --
            tipd_DQ10           => VitalZeroDelay01, --
            tipd_DQ11           => VitalZeroDelay01, --
            tipd_DQ12           => VitalZeroDelay01, --
            tipd_DQ13           => VitalZeroDelay01, --
            tipd_DQ14           => VitalZeroDelay01, --

            tipd_DQ15           => VitalZeroDelay01, -- DQ15/A-1

            tipd_CENeg          => VitalZeroDelay01,
            tipd_OENeg          => VitalZeroDelay01,
            tipd_WENeg          => VitalZeroDelay01,
            tipd_RESETNeg       => VitalZeroDelay01,
            tipd_WPNeg          => VitalZeroDelay01,--WP#/ACC
            tipd_BYTENeg        => VitalZeroDelay01,

            -- tpd delays
            tpd_A0_DQ0          => UnitDelay01,--tACC
            tpd_A0_DQ1          => UnitDelay01,--tPACC
            tpd_CENeg_DQ0       => UnitDelay01Z,
            --(tCE,tCE,tDF,-,tDF
            tpd_OENeg_DQ0       => UnitDelay01Z,
            --(tOE,tOE,tDF,-,tDF
            tpd_RESETNeg_DQ0    => UnitDelay01Z,
            --(-,-,0,-,0,-)
            tpd_CENeg_RY        => UnitDelay01, --tBUSY
            tpd_WENeg_RY        => UnitDelay01, --tBUSY

            --tsetup values
            tsetup_A0_CENeg     => UnitDelay,  --tAS edge \
            tsetup_A0_OENeg     => UnitDelay,  --tASO edge \
            tsetup_DQ0_CENeg    => UnitDelay,  --tDS edge /

            --thold values
            thold_CENeg_RESETNeg=> UnitDelay,   --tRH  edge /
            thold_OENeg_WENeg   => UnitDelay,   --tOEH edge /
            thold_A0_CENeg      => UnitDelay,   --tAH  edge \
            thold_A0_OENeg      => UnitDelay,   --tAHT edge \
            thold_DQ0_CENeg     => UnitDelay,   --tDH edge /
            thold_WENeg_OENeg   => UnitDelay,   --tGHVL edge /

            --tpw values: pulse width
            tpw_RESETNeg_negedge=> UnitDelay, --tRP
            tpw_OENeg_posedge   => UnitDelay, --tOEPH
            tpw_WENeg_negedge   => UnitDelay, --tWP
            tpw_WENeg_posedge   => UnitDelay, --tWPH
            tpw_CENeg_negedge   => UnitDelay, --tCP
            tpw_CENeg_posedge   => UnitDelay, --tCEPH
            tpw_A0_negedge      => UnitDelay, --tWC tRC
            -- tdevice values: values for internal delays
                --Effective Write Buffer Program Operation  tWHWH1
            tdevice_WBPB        => 11 us,
                --Program Operation
            tdevice_POB         => 100 us,
                --Sector Erase Operation    tWHWH2
            tdevice_SEO         => 500 ms,
                --Timing Limit Exceeded
            tdevice_HANG        => 400 ms, --?
                --program/erase suspend timeout
            tdevice_START_T1    => 5 us,
                --sector erase command sequence timeout
            tdevice_CTMOUT      => 50 us,
                --device ready after Hardware reset(during embeded algorithm)
            tdevice_READY       => 20 us, --tReady

            -- generic control parameters
            InstancePath        => DefaultInstancePath,
            TimingChecksOn      => TRUE,--DefaultTimingChecks,
            MsgOn               => DefaultMsgOn,
            XOn                 => DefaultXon,
            -- memory file to be loaded
            mem_file_name       => mem_file,
            prot_file_name      => prot_file ,
            secsi_file_name     => secsi_file,

            UserPreload         => UserPreload,
            LongTimming         => LongTimming,
            -- For FMF SDF technology file usage
            TimingModel         => "AM29LV640MH90R" -- TimingModel
        )
        PORT MAP(
            A21        => T_A(21), --
            A20        => T_A(20), --
            A19        => T_A(19), --
            A18        => T_A(18), --
            A17        => T_A(17), --
            A16        => T_A(16), --
            A15        => T_A(15), --
            A14        => T_A(14), --
            A13        => T_A(13), --address
            A12        => T_A(12), --lines
            A11        => T_A(11), --
            A10        => T_A(10), --
            A9         => T_A(9), --
            A8         => T_A(8), --
            A7         => T_A(7), --
            A6         => T_A(6), --
            A5         => T_A(5),--
            A4         => T_A(4),--
            A3         => T_A(3), --
            A2         => T_A(2), --
            A1         => T_A(1), --
            A0         => T_A(0), --

            DQ15       => T_DQ(15), -- DQ15/A-1
            DQ14       => T_DQ(14), --
            DQ13       => T_DQ(13), --
            DQ12       => T_DQ(12), --
            DQ11       => T_DQ(11), --
            DQ10       => T_DQ(10), --
            DQ9        => T_DQ(9), -- data
            DQ8        => T_DQ(8), -- lines
            DQ7        => T_DQ(7), --
            DQ6        => T_DQ(6), --
            DQ5        => T_DQ(5), --
            DQ4        => T_DQ(4), --
            DQ3        => T_DQ(3), --
            DQ2        => T_DQ(2), --
            DQ1        => T_DQ(1), --
            DQ0        => T_DQ(0), --

            CENeg      => T_CENeg,
            OENeg      => T_OENeg,
            WENeg      => T_WENeg,
            RESETNeg   => T_RESETNeg,
            WPNeg      => T_WPNeg, --WP#/ACC
            BYTENeg    => T_BYTENeg,
            RY         => T_RY  --RY/BY#
        );

    ---------------------------------------------------------------------------
    --protected sector
    ---------------------------------------------------------------------------
    ProtSecNum <= SecNum WHEN  TimingModel(11) = 'H' ELSE
                  0 ;--  WHEN  TimingModel = "AM29LV128ML93R"

    pwron <= '0', '1' after 1 ns;

--At the end of the simulation, if ErrorInTest='0' there were no errors
err_ctrl : PROCESS ( check_err  )
    BEGIN
        IF check_err = '1' THEN
            ErrorInTest <= '1';
        END IF;
    END PROCESS err_ctrl;

tb  :PROCESS

    --------------------------------------------------------------------------
    --= PROCEDURE to select TC
    -- can be modified to read TC list from file, or to generate random list
    --------------------------------------------------------------------------
    PROCEDURE   Pick_TC
        (Model   :  IN  STRING  := "AM29LV640MH90R"  )
    IS
    BEGIN
        IF TC_cnt < tc(TS_cnt) THEN
            TC_cnt := TC_cnt+1;
        ELSE
            TC_cnt:=1;
            IF TS_cnt<30 THEN
                TS_cnt := TS_cnt+1;
            ELSE
                -- end test
                IF ErrorInTest='0' THEN
                    REPORT "Test Ended without errors"
                    SEVERITY note;
                ELSE
                    REPORT "There were errors in test"
                    SEVERITY note;
                END IF;
                WAIT;
            END IF;
        END IF;
    END PROCEDURE Pick_TC;

   ---------------------------------------------------------------------------
    --bus commands, device specific implementation
    ---------------------------------------------------------------------------
    TYPE bus_type IS (bus_idle,
                      bus_standby,  --CE# deasseretd, others are don't care
                      bus_enable,   --CE# asserted, others deasserted
                      bus_output_disable,
                      bus_reset,
                      bus_write,
                      bus_read);

    --bus drive for specific command sequence cycle
    PROCEDURE bus_cycle(
        bus_cmd :IN   bus_type := bus_idle;
        byte    :IN   boolean                      ;
        data    :IN   INTEGER RANGE -2 TO MaxData  := -2; -- -1 for all Z
        dataHi  :IN   INTEGER RANGE -2 TO MaxData  := -2; -- -2 for ignore
        sector  :IN   INTEGER RANGE -1 TO SecNum   := -1; -- -1 for ignore addr
        address :IN   NATURAL RANGE  0 TO SecSize  := 0;
        disable :IN   boolean                      := false;
        violate :IN   boolean                      := false;
        tm      :IN   TIME                         := 10 ns)
    IS

        VARIABLE tmp : std_logic_vector(15 downto 0);
    BEGIN

        IF data=-1 THEN -- HiZ
            T_DQ(7 downto 0) <= (OTHERS => 'Z');
        END IF;

        IF (NOT byte)THEN --word access
            IF dataHi=-1 THEN -- HiZ
                T_DQ(15 downto 8) <= (OTHERS => 'Z');
            END IF;
            T_BYTENeg <= '1';
        ELSE                 --byte access
            T_BYTENeg <= '0';
            T_DQ(14 downto 8) <= (OTHERS => 'Z');
        END IF;

        IF sector > -1 THEN
            T_A(HiAddrBit downto 15) <= to_slv(sector, HiAddrbit-14);
            tmp := to_slv(address, 16);
            IF byte THEN
                T_A(14 downto 0) <= tmp(15 downto 1);
                T_DQ(15) <= tmp(0);
            ELSE
                T_A(14 downto 0) <= tmp(14 downto 0);
            END IF;

        END IF;

        wait for 1 ns;

        CASE bus_cmd IS
            WHEN bus_output_disable    =>
                T_OENeg    <= '1';
                WAIT FOR 20 ns;

            WHEN bus_idle       =>
                T_RESETNeg <= '1';
                T_WENeg    <= '1';
                T_CENeg    <= '1';
                T_OENeg    <= '1';
                IF disable THEN
                    T_WPNeg <= '0';
                ELSE
                    T_WPNeg <= '1';
                END IF;
                WAIT FOR 30 ns;

            WHEN bus_standby             =>
                T_CENeg    <= '1';
                WAIT FOR 30 ns;

            WHEN bus_reset               =>
                T_RESETNeg <= '0', '1' AFTER tm ;
                -- WAIT FOR 500 ns should follow this bus cmd for reset to
                --complete
                WAIT FOR 30 ns;

            WHEN bus_enable              =>
                T_WENeg    <= '1' AFTER 50 ns;   ---
                T_CENeg    <= '0' AFTER 50 ns;   ---
                T_OENeg    <= '1' AFTER 30 ns;   ---

                WAIT FOR tm ;

            WHEN bus_write  =>
                T_OENeg <= '1' ;-- AFTER 5 ns;
                T_CENeg <= '0' AFTER 10 ns ;
                T_WENeg <= '0' AFTER 20 ns;

                IF data>-1 THEN
                    T_DQ(7 downto 0) <= to_slv(data,8);
                END IF;
                IF NOT byte THEN
                    IF dataHi>-1 THEN
                        T_DQ(15 downto 8) <= to_slv(dataHi,8);
                    END IF;
                END IF;

                IF violate THEN
                    T_WENeg <= '1';
                    WAIT FOR 50 ns;
                    T_WENeg <= '0', '1' AFTER tm;