📄 testbench.vhd
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-------------------------------------------------------------------------------- File name : testbench_640.vhd--------------------------------------------------------------------------------- Copyright (C) 2003 AMD.---- MODIFICATION HISTORY :---- version: | author: | mod date: | changes made:-- V0.1 M.Marinkovic 11 July 03 Initial-- v0.2 M.Marinkovic 28 Aug 03 Changed protected sector selection----------------------------------------------------------------------------------- PART DESCRIPTION:---- Description:-- Generic test enviroment for verification of AMD flash memory-- VITAL models.my_mem----------------------------------------------------------------------------------- Note: VHDL code formating not done-- For High/Low sector protection selection change:-- TimingModel constant and TimingModel generic value---------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;--USE IEEE.VITAL_timing.ALL;--USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL;LIBRARY VITAL2000; USE VITAL2000.vital_timing.ALL; USE VITAL2000.vital_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;LIBRARY work; USE work.amd_tc_pkg.ALL;--------------------------------------------------------------------------------- ENTITY DECLARATION-------------------------------------------------------------------------------ENTITY testbench_640 ISEND testbench_640;--------------------------------------------------------------------------------- ARCHITECTURE DECLARATION-------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of testbench_640 IS COMPONENT my_mem GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A21 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1 tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC tipd_BYTENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC tpd_A0_DQ1 : VitalDelayType01 := UnitDelay01;--tPACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tCE,tCE,tDF,-,tDF,-) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(-,-,0,-,0,-) tpd_CENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY tpd_WENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY --tsetup values tsetup_A0_CENeg : VitalDelayType := UnitDelay; --tAS edge \ tsetup_A0_OENeg : VitalDelayType := UnitDelay; --tASO edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / --thold values thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / thold_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH edge / thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge \ thold_A0_OENeg : VitalDelayType := UnitDelay; --tAHT edge \ thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge / thold_WENeg_OENeg : VitalDelayType := UnitDelay; --tGHWL edge / --tpw values: pulse width tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP tpw_OENeg_posedge : VitalDelayType := UnitDelay; --tOEPH tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCEPH tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC -- tdevice values: values for internal delays --Effective Write Buffer Program Operation tWHWH1 tdevice_WBPB : VitalDelayType := 11 us; --Program Operation tdevice_POB : VitalDelayType := 100 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 500 ms; --Timing Limit Exceeded tdevice_HANG : VitalDelayType := 400 ms; --? --program/erase suspend timeout tdevice_START_T1 : VitalDelayType := 5 us; --sector erase command sequence timeout tdevice_CTMOUT : VitalDelayType := 50 us; --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := 20 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING ;--:= "am29lv640m.mem"; prot_file_name : STRING ;--:= "am29lv640m_prot.mem"; secsi_file_name : STRING ;--:= "am29lv_secsi.mem"; UserPreload : BOOLEAN ;--:= TRUE; LongTimming : BOOLEAN ;--:= TRUE; -- For FMF SDF technology file usage TimingModel : STRING --:= "AM29LV640MH90R" ); PORT ( A21 : IN std_logic := 'U'; -- A20 : IN std_logic := 'U'; -- A19 : IN std_logic := 'U'; -- A18 : IN std_logic := 'U'; -- A17 : IN std_logic := 'U'; -- A16 : IN std_logic := 'U'; -- A15 : IN std_logic := 'U'; -- A14 : IN std_logic := 'U'; -- A13 : IN std_logic := 'U'; --address A12 : IN std_logic := 'U'; --lines A11 : IN std_logic := 'U'; -- A10 : IN std_logic := 'U'; -- A9 : IN std_logic := 'U'; -- A8 : IN std_logic := 'U'; -- A7 : IN std_logic := 'U'; -- A6 : IN std_logic := 'U'; -- A5 : IN std_logic := 'U'; -- A4 : IN std_logic := 'U'; -- A3 : IN std_logic := 'U'; -- A2 : IN std_logic := 'U'; -- A1 : IN std_logic := 'U'; -- A0 : IN std_logic := 'U'; -- DQ15 : INOUT std_logic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_logic := 'U'; -- DQ13 : INOUT std_logic := 'U'; -- DQ12 : INOUT std_logic := 'U'; -- DQ11 : INOUT std_logic := 'U'; -- DQ10 : INOUT std_logic := 'U'; -- DQ9 : INOUT std_logic := 'U'; -- data DQ8 : INOUT std_logic := 'U'; -- lines DQ7 : INOUT std_logic := 'U'; -- DQ6 : INOUT std_logic := 'U'; -- DQ5 : INOUT std_logic := 'U'; -- DQ4 : INOUT std_logic := 'U'; -- DQ3 : INOUT std_logic := 'U'; -- DQ2 : INOUT std_logic := 'U'; -- DQ1 : INOUT std_logic := 'U'; -- DQ0 : INOUT std_logic := 'U'; -- CENeg : IN std_logic := 'U'; OENeg : IN std_logic := 'U'; WENeg : IN std_logic := 'U'; RESETNeg : IN std_logic := 'U'; WPNeg : IN std_logic := 'U'; --WP#/ACC BYTENeg : IN std_logic := 'U'; RY : OUT std_logic := 'U' --RY/BY# ); END COMPONENT; FOR ALL: my_mem USE ENTITY WORK.my_mem(VHDL_BEHAVIORAL); --------------------------------------------------------------------------- --memory configuration --------------------------------------------------------------------------- CONSTANT MaxData : NATURAL := 16#FF#; --255; CONSTANT SecSize : NATURAL := 16#FFFF#; --65535 CONSTANT SecSiSize : NATURAL := 255; CONSTANT SecNum : NATURAL := 127; CONSTANT HiAddrBit : NATURAL := 21; --Address of the Protected Sector-- CONSTANT ProtSecNum : NATURAL := SecNum; --------------------------------------------------------------------------- --model configuration --------------------------------------------------------------------------- CONSTANT mem_file : STRING := "am29lv640m.mem"; CONSTANT prot_file : STRING := "am29lv640m_prot.mem"; CONSTANT secsi_file : STRING := "am29lv_secsi.mem"; CONSTANT UserPreload : boolean := TRUE; CONSTANT DebugInfo : boolean := FALSE; CONSTANT LongTimming : boolean := TRUE; CONSTANT TimingModel : STRING := "MY_MEM";
-- "AM29LV640MH90R";--High sect prot. -- "AM29LV128ML93R";--Low sect. prot. --------------------------------------------------------------------------- SIGNAL ProtSecNum : NATURAL := SecNum ; --Flash Memory Array TYPE SecType IS ARRAY (0 TO SecSize) OF INTEGER RANGE -1 TO MaxData; TYPE MemArray IS ARRAY (0 TO SecNum) OF SecType; --Common Flash Interface Query codes TYPE CFItype IS ARRAY (16#10# TO 16#50#) OF NATURAL RANGE 0 TO 16#FF#; --SecSi Sector TYPE SecSiType IS ARRAY ( 0 TO SecSiSize) OF INTEGER RANGE -1 TO MaxData; --------------------------------------------------------------------------- -- memory declaration --------------------------------------------------------------------------- -- -- Mem(SecAddr)(Address).... SHARED VARIABLE Mem : MemArray := (OTHERS => (OTHERS=> MaxData)); SHARED VARIABLE CFI_array : CFItype :=(OTHERS=>0); SHARED VARIABLE SecSi : SecSiType :=(OTHERS=>0); --command sequence SHARED VARIABLE cmd_seq : cmd_seq_type; SIGNAL status : status_type := none; SIGNAL sts_check : std_logic_vector(7 downto 0); SIGNAL check_err : std_logic := '0'; SIGNAL ErrorInTest : std_logic := '0'; -- ---------------------------------------------------------------------------- --Personality module: -- -- instanciates the DUT module and adapts generic test signals to it -- TBD: block port ---------------------------------------------------------------------------- --DUT port SIGNAL T_DQ : std_logic_vector(15 downto 0) := (OTHERS=>'U'); SIGNAL T_A : std_logic_vector(HiAddrBit downto 0) := (OTHERS=>'U'); SIGNAL T_RESETNeg : std_logic := 'U'; SIGNAL T_CENeg : std_logic := 'U'; SIGNAL T_WENeg : std_logic := 'U'; SIGNAL T_OENeg : std_logic := 'U'; SIGNAL T_WPNeg : std_logic := 'U'; SIGNAL T_BYTENeg : std_logic := 'U'; SIGNAL T_RY : std_logic := 'U'; --------------------------------------------------------------------------- -- --------------------------------------------------------------------------- --SecSi ProtectionStatus SHARED VARIABLE FactoryProt : std_logic := '1'; --Sector Protection Status SHARED VARIABLE Sec_Prot : std_logic_vector (SecNum downto 0) := (OTHERS => '0'); SHARED VARIABLE Sect : NATURAL RANGE 0 TO SecNum := 0; SHARED VARIABLE Addr : NATURAL RANGE 0 TO SecSize := 0; SHARED VARIABLE WriteData : NATURAL RANGE 0 TO MaxData := 0; --CONSTANT --timming parameters CONSTANT RESETNeg_pw : time := 500 ns; --tRP SIGNAL pwron : std_logic := '0'; SIGNAL Tseries : NATURAL; SIGNAL Tcase : NATURAL; SHARED VARIABLE ts_cnt : NATURAL RANGE 1 TO 30:=1; -- testseries counter⌨️ 快捷键说明
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