am29lv160d.v

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

*/

  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ0) = tpd_OENeg_DQ0;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ1) = tpd_OENeg_DQ1;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ2) = tpd_OENeg_DQ2;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ3) = tpd_OENeg_DQ3;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ4) = tpd_OENeg_DQ4;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ5) = tpd_OENeg_DQ5;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ6) = tpd_OENeg_DQ6;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ7) = tpd_OENeg_DQ7;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ8) = tpd_OENeg_DQ8;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ9) = tpd_OENeg_DQ9;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ10) = tpd_OENeg_DQ10;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ11) = tpd_OENeg_DQ11;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ12) = tpd_OENeg_DQ12;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ13) = tpd_OENeg_DQ13;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ14) = tpd_OENeg_DQ14;
  if (~SWITCH || (SWITCH && FROMOE))
    (OENeg *> DQ15) = tpd_OENeg_DQ15;

//  if (~BYTENeg) (DQ15 *> DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7) = tpd_DQ15_DQ0;

  if (~BYTENeg) (DQ15 *> DQ0) = tpd_DQ15_DQ0;
  if (~BYTENeg) (DQ15 *> DQ1) = tpd_DQ15_DQ1;
  if (~BYTENeg) (DQ15 *> DQ2) = tpd_DQ15_DQ2;
  if (~BYTENeg) (DQ15 *> DQ3) = tpd_DQ15_DQ3;
  if (~BYTENeg) (DQ15 *> DQ4) = tpd_DQ15_DQ4;
  if (~BYTENeg) (DQ15 *> DQ5) = tpd_DQ15_DQ5;
  if (~BYTENeg) (DQ15 *> DQ6) = tpd_DQ15_DQ6;
  if (~BYTENeg) (DQ15 *> DQ7) = tpd_DQ15_DQ7;

//  if (BYTENeg) (BYTENeg *> DQ0, DQ1, DQ2 , DQ3 , DQ4 , DQ5 , DQ6 , DQ7,
//              DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15) = tpd_BYTENeg_DQ0;

  if (BYTENeg) (BYTENeg *> DQ8) = tpd_BYTENeg_DQ8;
  if (BYTENeg) (BYTENeg *> DQ9) = tpd_BYTENeg_DQ9;
  if (BYTENeg) (BYTENeg *> DQ10) = tpd_BYTENeg_DQ10;
  if (BYTENeg) (BYTENeg *> DQ11) = tpd_BYTENeg_DQ11;
  if (BYTENeg) (BYTENeg *> DQ12) = tpd_BYTENeg_DQ12;
  if (BYTENeg) (BYTENeg *> DQ13) = tpd_BYTENeg_DQ13;
  if (BYTENeg) (BYTENeg *> DQ14) = tpd_BYTENeg_DQ14;
  if (BYTENeg) (BYTENeg *> DQ15) = tpd_BYTENeg_DQ15;

//  if (~RESETNeg) (RESETNeg *> DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7,
//            DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15) = tpd_RESETNeg_DQ0;


  if (~RESETNeg) (RESETNeg *> DQ0) = tpd_RESETNeg_DQ0;
  if (~RESETNeg) (RESETNeg *> DQ1) = tpd_RESETNeg_DQ1;
  if (~RESETNeg) (RESETNeg *> DQ2) = tpd_RESETNeg_DQ2;
  if (~RESETNeg) (RESETNeg *> DQ3) = tpd_RESETNeg_DQ3;
  if (~RESETNeg) (RESETNeg *> DQ4) = tpd_RESETNeg_DQ4;
  if (~RESETNeg) (RESETNeg *> DQ5) = tpd_RESETNeg_DQ5;
  if (~RESETNeg) (RESETNeg *> DQ6) = tpd_RESETNeg_DQ6;
  if (~RESETNeg) (RESETNeg *> DQ7) = tpd_RESETNeg_DQ7;
  if (~RESETNeg) (RESETNeg *> DQ8) = tpd_RESETNeg_DQ8;
  if (~RESETNeg) (RESETNeg *> DQ9) = tpd_RESETNeg_DQ9;
  if (~RESETNeg) (RESETNeg *> DQ10) = tpd_RESETNeg_DQ10;
  if (~RESETNeg) (RESETNeg *> DQ11) = tpd_RESETNeg_DQ11;
  if (~RESETNeg) (RESETNeg *> DQ12) = tpd_RESETNeg_DQ12;
  if (~RESETNeg) (RESETNeg *> DQ13) = tpd_RESETNeg_DQ13;
  if (~RESETNeg) (RESETNeg *> DQ14) = tpd_RESETNeg_DQ14;
  if (~RESETNeg) (RESETNeg *> DQ15) = tpd_RESETNeg_DQ15;

//  if (~BYTENeg) (BYTENeg *> DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15) = tpd_BYTENeg_DQ0;

  if (~BYTENeg) (BYTENeg *> DQ8) = tpd_BYTENeg_DQ8;
  if (~BYTENeg) (BYTENeg *> DQ9) = tpd_BYTENeg_DQ9;
  if (~BYTENeg) (BYTENeg *> DQ10) = tpd_BYTENeg_DQ10;
  if (~BYTENeg) (BYTENeg *> DQ11) = tpd_BYTENeg_DQ11;
  if (~BYTENeg) (BYTENeg *> DQ12) = tpd_BYTENeg_DQ12;
  if (~BYTENeg) (BYTENeg *> DQ13) = tpd_BYTENeg_DQ13;
  if (~BYTENeg) (BYTENeg *> DQ14) = tpd_BYTENeg_DQ14;
  if (~BYTENeg) (BYTENeg *> DQ15) = tpd_BYTENeg_DQ15;



//for RY signal
  (WENeg => RY)     = tpd_WENeg_RY;
  (CENeg => RY)     = tpd_CENeg_RY;


////////////////////////////////////////////////////////////////////////////////
// Timing Violation                                                           //
////////////////////////////////////////////////////////////////////////////////

        $setup ( A0 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A1 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A2 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A3 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A4 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A5 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A6 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A7 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A8 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A9 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A10 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A11 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A12 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A13 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A14 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A15 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A16 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A17 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A18 , negedge CENeg, tsetup_A0_CENeg, Viol);
        $setup ( A19 , negedge CENeg, tsetup_A0_CENeg, Viol);

        $setup ( A0 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A1 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A2 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A3 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A4 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A5 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A6 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A7 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A8 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A9 , negedge WENeg,  tsetup_A0_CENeg, Viol);
        $setup ( A10 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A11 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A12 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A13 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A14 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A15 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A16 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A17 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A18 , negedge WENeg, tsetup_A0_CENeg, Viol);
        $setup ( A19 , negedge WENeg, tsetup_A0_CENeg, Viol);

        $setup ( BYTENeg , negedge WENeg , tsetup_A0_CENeg, Viol);//31/10/03

        $setup ( DQ0 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ1 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ2 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ3 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ4 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ5 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ6 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ7 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ8 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ9 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ10 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ11 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ12 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ13 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ14 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ15 , posedge CENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ0 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ1 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ2 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ3 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ4 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ5 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ6 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ7 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ8 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ9 , posedge WENeg &&& deg,  tsetup_A0_CENeg, Viol);
        $setup ( DQ10 , posedge WENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ11 , posedge WENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ12 , posedge WENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ13 , posedge WENeg &&& deg, tsetup_A0_CENeg, Viol);
        $setup ( DQ14 , posedge WENeg &&& deg, tsetup_A0_CENeg, Viol);  
        $setup ( DQ15 , posedge WENeg &&& deg, tsetup_A0_CENeg, Viol); 
       
        $setup ( CENeg   , negedge WENeg , tsetup_A0_CENeg, Viol);                             
        $setup ( BYTENeg , negedge CENeg , tsetup_A0_CENeg, Viol);
        $setup ( OENeg   , negedge WENeg , tsetup_A0_CENeg, Viol);// 31/10/03

        $setup ( BYTENeg , negedge WENeg , tsetup_A0_CENeg, Viol);//check
        $setup ( OENeg   , negedge WENeg , tsetup_A0_CENeg, Viol);//check

        $hold ( posedge RESETNeg &&& (CENeg===1), CENeg , thold_CENeg_RESETNeg, Viol);
        $hold ( posedge RESETNeg &&& (OENeg===1), OENeg , thold_CENeg_RESETNeg, Viol);
        $hold ( posedge RESETNeg &&& (WENeg===1), WENeg , thold_CENeg_RESETNeg, Viol);
        $hold ( posedge OENeg, WENeg , thold_WENeg_OENeg, Viol);
        $hold ( posedge WENeg, OENeg , thold_OENeg_WENeg, Viol);
        $hold ( posedge WENeg, CENeg , thold_WENeg_OENeg, Viol);
        $hold ( negedge CENeg, BYTENeg, thold_BYTENeg_CENeg, Viol);
        $hold ( negedge WENeg, BYTENeg, thold_A0_CENeg, Viol);//??
        $hold ( posedge OENeg, CENeg , thold_WENeg_OENeg, Viol);

        $hold ( negedge CENeg, A0 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A1 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A2 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A3 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A4 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A5 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A6 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A7 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A8 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A9 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A10 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A11 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A12 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A13 , thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A14 , thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A15 , thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A16 , thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A17 , thold_A0_CENeg, Viol);     
        $hold ( negedge CENeg, A18 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, A19 , thold_A0_CENeg, Viol);

        $hold ( negedge WENeg, A0 ,  thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A1 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A2 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A3 ,  thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A4 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A5 ,  thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A6 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A7 ,  thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A8 ,  thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A9 ,  thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A10 , thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A11 , thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A12 , thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A13 , thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A14 , thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A15 , thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A16 , thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A17 , thold_A0_CENeg, Viol);     
        $hold ( negedge WENeg, A18 , thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, A19 , thold_A0_CENeg, Viol);

        $hold ( negedge WENeg, BYTENeg, thold_A0_CENeg, Viol);

        $hold ( negedge CENeg, DQ0 ,  thold_DQ0_CENeg, Viol);
        $hold ( negedge CENeg, DQ1 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ2 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ3 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ4 ,  thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, DQ5 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ6 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ7 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ8 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ9 ,  thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ10 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, DQ11 , thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ12 , thold_A0_CENeg, Viol);  
        $hold ( negedge CENeg, DQ13 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, DQ14 , thold_A0_CENeg, Viol);
        $hold ( negedge CENeg, DQ15 ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ0  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ1  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ2  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ3  ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ4  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ5  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ6  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ7  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ8  ,   thold_A0_CENeg, Viol);  
        $hold ( negedge WENeg, DQ9  ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ10 ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ11 ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ12 ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ13 ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ14 ,   thold_A0_CENeg, Viol);
        $hold ( negedge WENeg, DQ15 ,   thold_A0_CENeg, Viol);

        $width (negedge RESETNeg, tpw_RESETNeg_negedge);
        $width (posedge WENeg, tpw_WENeg_posedge);
        $width (negedge WENeg, tpw_WENeg_negedge);
        $width (posedge CENeg, tpw_CENeg_posedge);
        $width (negedge CENeg, tpw_CENeg_negedge);
        $width (negedge A0, tpw_A0_negedge);//ok
        $width (posedge A0, tpw_A0_negedge);//ok

    endspecify

////////////////////////////////////////////////////////////////////////////////
// Main Behavior Block                                                        //
////////////////////////////////////////////////////////////////////////////////

// FSM states
 parameter RESET           =6'd0;
 parameter Z001            =6'd1;
 parameter PREL_SETBWB     =6'd2;
 parameter PREL_ULBYPASS   =6'd3;
 parameter CFI_U           =6'd4;
 parameter CFI             =6'd5;
 parameter AS              =6'd6;
 parameter A0SEEN          =6'd7;
 parameter C8              =6'd8;
 parameter C8_Z001         =6'd9;
 parameter C8_PREL         =6'd10;
 parameter ERS             =6'd11;
 parameter SERS            =6'd12;
 parameter ESPS            =6'd13;
 parameter SERS_EXEC       =6'd14;
 parameter ESP             =6'd15;
 parameter ESP_Z001        =6'd16;
 parameter ESP_PREL        =6'd17;
 parameter ESP_CFI_U       =6'd18;
 parameter ESP_CFI         =6'd19;
 parameter ESP_A0SEEN      =6'd20;
 parameter ESP_AS          =6'd21;
 parameter PGMS            =6'd22;

 reg [5:0] current_state;
 reg [5:0] next_state;

 reg deq;

    integer tmp1,tmp2,tmp3;
    integer sector_preload[0:MemSize];
    reg     sector_prot[0:SecNum+SubSecNum];

    always @(DIn, DOut)
    begin
        if (DIn==DOut)
            deq=1'b1;
        else
            deq=1'b0;
    end
    // check when data is generated from