am29lv160d.vhd

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

                        next_state <= AS;
                    ELSIF (A_PAT_1 AND (DataLo = 16#A0#)) THEN
                        next_state <= A0SEEN;
                    ELSIF (A_PAT_1 AND (DataLo = 16#80#)) THEN
                        next_state <= C8;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN PREL_ULBYPASS  =>
                IF falling_edge(write) THEN
                    IF (DataLo = 16#20#) THEN
                        next_state <= PREL_ULBYPASS;
                    ELSIF (DataLo = 16#98#) THEN
                        next_state <= CFI_U;
                    ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN
                        next_state <= AS;
                    ELSIF (A_PAT_1 AND (DataLo = 16#A0#)) THEN
                        next_state <= A0SEEN;
                    ELSIF (A_PAT_1 AND (DataLo = 16#80#)) THEN
                        next_state <= C8_PREL;
                    ELSE
                        next_state <= PREL_ULBYPASS;
                    END IF;
                END IF;

            WHEN CFI_U          =>
                IF falling_edge(write) THEN
                    IF (DataLo = 16#F0#) THEN
                        next_state <= RESET;
                    ELSE
                        next_state <=  CFI_U;
                    END IF;
                END IF;

            WHEN CFI            =>
                IF falling_edge(write) THEN
                    IF (Addr = 16#55#) AND (DataLo = 16#98#) THEN
                        next_state <= CFI;
                    ELSIF (DataLo = 16#F0#) THEN
                        next_state <= RESET;
                    ELSE
                        next_state <=  CFI;
                    END IF;
                END IF;

            WHEN AS             =>
                IF falling_edge(write) THEN
                    IF (DataLo = 16#F0#) THEN
                        next_state <= RESET;
                    ELSE
                        next_state <= AS;
                    END IF;
                END IF;

            WHEN A0SEEN         =>
                IF falling_edge(write) THEN
                    next_state <= PGMS;
                ELSE
                    next_state <= A0SEEN;
                END IF;

            WHEN C8             =>
                IF falling_edge(write) THEN
                    IF PATTERN_1 THEN
                        next_state <= C8_Z001;
                    ELSIF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN C8_Z001        =>
                IF falling_edge(write) THEN
                    IF PATTERN_2 THEN
                        next_state <= C8_PREL;
                    ELSIF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN C8_PREL        =>
                IF falling_edge(write) THEN
                    IF A_PAT_1 AND DataLo = 16#10# THEN
                        next_state <= ERS;
                    ELSIF DataLo = 16#30# THEN
                        next_state <= SERS;
                    ELSIF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN ERS            =>
                IF rising_edge(EDONE) OR falling_edge(EERR) THEN
                    IF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN SERS           =>
                IF CTMOUT_out = '1' AND CTMOUT_out'EVENT THEN
                    next_state <= SERS_EXEC;
                ELSIF falling_edge(write) THEN
                    IF (DataLo = 16#B0#) THEN
                        next_state <= ESPS; -- ESP according to datasheet
                    ELSIF (DataLo = 16#30#) THEN
                        next_state <= SERS;
                    ELSIF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;--C8_PREL;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN ESPS           =>
                IF (START_T1_out = '1') THEN
                    next_state <= ESP;
                END IF;

            WHEN SERS_EXEC      =>
                IF rising_edge(EDONE) OR falling_edge(EERR) THEN
                    IF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;
                    ELSE
                        next_state <= RESET;
                    END IF;
                ELSIF EERR /= '1' THEN
                    IF falling_edge(write) THEN
                        IF DataLo = 16#B0# THEN
                            next_state <= ESPS;
                        END IF;
                    END IF;
                END IF;

            WHEN ESP            =>
                IF falling_edge(write) THEN
                    IF DataLo = 16#30# THEN
                        next_state <= SERS_EXEC;
                    ELSIF ULBYPASS = '1' THEN
                        IF DataLo = 16#20# THEN
                            null;
                        ELSIF DataLo = 16#98# THEN
                            next_state <= ESP_CFI_U;
                        ELSIF A_PAT_1 AND DataLo = 16#A0# THEN
                            next_state <= ESP_A0SEEN;
                        ELSIF A_PAT_1 AND DataLo = 16#90# THEN
                            next_state <= ESP_AS;
                        END IF;
                    ELSE
                        IF Addr = 16#55# AND DataLo = 16#98# THEN
                            next_state <= ESP_CFI;
                        ELSIF PATTERN_1 THEN
                            next_state <= ESP_Z001;
                        END IF;
                    END IF;
                END IF;

            WHEN ESP_Z001       =>
                IF falling_edge(write) THEN
                    IF PATTERN_2 THEN
                        next_state <= ESP_PREL;
                    ELSE
                        next_state <= ESP;
                    END IF;
                END IF;

            WHEN ESP_PREL       =>
                IF falling_edge(write) THEN
                    IF A_PAT_1 AND DataLo = 16#20# THEN
                        next_state <= ESP;
                    ELSIF A_PAT_1 AND DataLo = 16#A0# THEN
                        next_state <= ESP_A0SEEN;
                    ELSIF A_PAT_1 AND DataLo = 16#90# THEN
                        next_state <= ESP_AS;
                    ELSE
                        next_state <= ESP;
                    END IF;
                END IF;

            WHEN ESP_CFI_U      =>
                --reset ULBYPASS
                IF falling_edge(write) THEN
                    IF DataLo = 16#98# THEN
                        null;
                    ELSIF DataLo = 16#F0# THEN
                        next_state <= ESP;
                    END IF;
                END IF;

            WHEN ESP_CFI        =>
                IF falling_edge(write) THEN
                    IF Addr = 16#55# AND DataLo = 16#98# THEN
                        null;
                    ELSIF DataLo = 16#F0# THEN
                        next_state <= ESP;
                    ELSIF DataLo = 16#30# THEN
                        next_state <= SERS_EXEC;
                    ELSE
                        next_state <= ESP;
                    END IF;
                END IF;

            WHEN ESP_A0SEEN     =>
                IF falling_edge(write) THEN
                    next_state <= PGMS; --set ESP
                END IF;

            WHEN ESP_AS         =>
                IF falling_edge(write) THEN
                    IF DataLo = 16#F0# THEN
                        -- resret ULBYPASS
                        next_state <= ESP;
                    END IF;
                END IF;

            WHEN PGMS           =>
                IF rising_edge(PDONE) OR falling_edge(PERR) THEN
                    IF ESP_ACT = '1' THEN
                        next_state <= ESP;
                    ELSIF ULBYPASS = '1' THEN
                        next_state <= PREL_ULBYPASS;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

        END CASE;
        END IF;
END PROCESS StateGen;

    ---------------------------------------------------------------------------
    --FSM Output generation and general funcionality
    ---------------------------------------------------------------------------
    Functional : PROCESS(write, read, Addr, D_tmp0, D_tmp1, Address, SecAddr,
                         PDONE, EDONE, HANG, START_T1_out, CTMOUT_out, RST,
                          reseted, READY_out, gOE_n, current_state)

        --Common Flash Interface Query codes
        TYPE CFItype  IS ARRAY (16#10# TO 16#4C#) OF
                        NATURAL RANGE 0 TO 16#FF#;

        --Program
        TYPE WDataType IS ARRAY ( 0 TO 1) OF--n
                          INTEGER RANGE -1 TO MaxData;
        TYPE WAddrType IS ARRAY ( 0 TO 1) OF
                          INTEGER RANGE -1 TO SecSize;--n

        VARIABLE CFI_array   : CFItype   :=(OTHERS=>0);

        VARIABLE WData       : WDataType:=(OTHERS=>0);--n
        VARIABLE WAddr       : WAddrType:=(OTHERS=>-1);--n

        VARIABLE cnt         : NATURAL RANGE 0 TO 31 := 0;

        VARIABLE PATTERN_1   : boolean := FALSE;
        VARIABLE PATTERN_2   : boolean := FALSE;
        VARIABLE A_PAT_1     : boolean := FALSE;

        VARIABLE oe          : boolean := FALSE;
        --Status reg.
        VARIABLE Status      : std_logic_vector(7 downto 0) := (OTHERS=>'0');

        VARIABLE old_bit     : std_logic_vector(7 downto 0);
        VARIABLE new_bit     : std_logic_vector(7 downto 0);
        VARIABLE old_int     : INTEGER RANGE -1 to MaxData;
        VARIABLE new_int     : INTEGER RANGE -1 to MaxData;
        VARIABLE wr_cnt      : NATURAL RANGE 0 TO 31;

        --DATA  High Byte
        VARIABLE DataHi      : NATURAL RANGE 0 TO MaxData := 0;
        --DATA Low Byte
        VARIABLE DataLo      : NATURAL RANGE 0 TO MaxData := 0;

        VARIABLE temp        : std_logic_vector(7 downto 0);
    BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------
        IF falling_edge(write) THEN
            DataLo    := D_tmp0;
            DataHi    := D_tmp1;
            PATTERN_1 := (Addr = 16#555#) AND (DataLo = 16#AA#) ;
            PATTERN_2 := (Addr = 16#2AA#) AND (DataLo = 16#55#) ;
            A_PAT_1   := ((Addr = 16#555#)AND (ULBYPASS = '0')) OR 
                      (ULBYPASS = '1');
        END IF;
        oe := rising_edge(read) OR
        (read = '1' AND (Address'EVENT OR SecAddr'EVENT OR BYTENEg'EVENT));

        IF reseted = '1' THEN
        CASE current_state IS
            WHEN RESET          =>
                ESP_ACT   <= '0';

                IF falling_edge(write) THEN
                    IF ((Addr = 16#55#) AND (DataLo = 16#98#))THEN
                        ULBYPASS <= '0';
                    END IF;
                ELSIF oe THEN
                    IF Mem(SecAddr)(Address) = -1 THEN
                        DOut_zd(7 downto 0) <= (OTHERS=>'X');
                    ELSE
                        DOut_zd(7 downto 0) <= to_slv(Mem(SecAddr)(Address),8);
                    END IF;
                    IF BYTENeg = '1' THEN