am29lv160d.vhd

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

        Viol <= Violation;

        ASSERT Violation = '0'
            REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
            SEVERITY WARNING;
    END IF;
END PROCESS VITALTimingCheck;

    ----------------------------------------------------------------------------
    -- sequential process for reset control and FSM state transition
    ----------------------------------------------------------------------------
    StateTransition : PROCESS(next_state, RESETNeg, RST, READY_out, PDone,
                              EDone, PoweredUp)

        VARIABLE R  : std_logic := '0'; --prog or erase in progress
        VARIABLE E  : std_logic := '0'; --reset timming error

    BEGIN
        IF PoweredUp='1' THEN
        --Hardware reset timing control
            IF falling_edge(RESETNeg) THEN
                E := '0';
                IF (PDONE='0' OR EDONE='0') THEN
                    --if program or erase in progress
                    READY_in <= '1';
                    R :='1';
                ELSE
                    READY_in <= '0';
                    R:='0';         --prog or erase not in progress
                END IF;
            ELSIF rising_edge(RESETNeg) AND RST='1' THEN
                --RESET# pulse < tRP
                READY_in <= '0';
                R := '0';
                E := '1';
            END IF;

            IF  RESETNeg='1' AND ( R='0' OR (R='1' AND READY_out='1')) THEN
                current_state <= next_state;
                READY_in <= '0';
                E := '0';
                R := '0';
                reseted <= '1';

            ELSIF (R='0' AND RESETNeg='0' AND RST='0')OR
                  (R='1' AND RESETNeg='0' AND RST='0' AND READY_out='0')OR
                  (R='1' AND RESETNeg='1' AND RST='0' AND READY_out='0')OR
                  (R='1' AND RESETNeg='1' AND RST='1' AND READY_out='0') THEN
                --no state transition while RESET# low

                current_state <= RESET; --reset start
                reseted       <= '0';
            END IF;

        ELSE
            current_state <= RESET;      -- reset
            reseted       <= '0';
            E := '0';
            R := '0';
        END IF;

END PROCESS StateTransition;

    ---------------------------------------------------------------------------
    --Glitch Protection: Inertial Delay does not propagate pulses <5ns
    ---------------------------------------------------------------------------
    gWE_n <= WENeg AFTER 5 ns;
    gCE_n <= CENeg AFTER 5 ns;
    gOE_n <= OENeg AFTER 5 ns;

    --latch address on rising edge and data on falling edge  of write
    write_dc: PROCESS (gWE_n, gCE_n, gOE_n, RESETNeg, reseted)
    BEGIN
        IF RESETNeg /= '0' AND reseted = '1' THEN
            IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN
                write <= '1';
            ELSIF (gWE_n = '1' OR gCE_n = '1') AND gOE_n = '1' THEN
                write <= '0';
            ELSE
                write <= 'X';
            END IF;
        END IF;

        IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0') )THEN
            read <= '1';
        ELSE
            read <= '0';
        END IF;

    END PROCESS write_dc;

    ---------------------------------------------------------------------------
    --Process that reports warning when changes on signals WE#, CE#, OE# are
    --discarded
    ---------------------------------------------------------------------------
    PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n)
    BEGIN
        IF (WENeg'EVENT AND (gWE_n = WENeg)) OR
           (CENeg'EVENT AND (gCE_n = CENeg)) OR
           (OENeg'EVENT AND (gOE_n = OENeg)) THEN
            ASSERT false
                REPORT "Glitch detected on write control signals"
                SEVERITY warning;
        END IF;
    END PROCESS PulseWatch;

    ---------------------------------------------------------------------------
    --Latch address on falling edge of WE# or CE# what ever comes later
    --Latches data on rising edge of WE# or CE# what ever comes first
    -- also Write cycle decode
    ---------------------------------------------------------------------------
    BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, BYTENeg,
                             reseted)

        VARIABLE A_tmp  : NATURAL RANGE 0 TO 16#7FF#;
        VARIABLE SA_tmp : NATURAL RANGE 0 TO SecNum;
        VARIABLE A_tmp1 : NATURAL RANGE 0 TO SecSize;

        VARIABLE CE     : std_logic;
        VARIABLE i      : NATURAL;
    BEGIN
        IF reseted='1' THEN
            IF (falling_edge(WENeg) AND CENeg='0' AND OENeg = '1' ) OR
               (falling_edge(CENeg) AND          WENeg /= OENeg ) OR
               (falling_edge(OENeg) AND WENeg='1' AND CENeg = '0' ) OR
               ((A'EVENT OR (Din(15)'EVENT AND BYTENeg='0' AND
                 Din(15) /= Dout_zd(15)) OR BYTENeg'EVENT )
            AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN

                A_tmp :=  to_nat( A(10 downto 0) );--???????
                SA_tmp:=  to_nat( A(HiAddrBit downto 15));

                IF (BYTENeg = '0') THEN
                    A_tmp1 := to_nat( A(14 downto 0) & Din(15) );
                ELSE
                    A_tmp1 := to_nat( A(14 downto 0) & '0' );
                END IF;

            ELSIF (rising_edge(WENeg) OR rising_edge(CENeg)) 
                AND write = '1' THEN
                D_tmp0 <= to_nat(Din(7 downto 0));
                IF BYTENeg = '1' THEN
                    D_tmp1 <= to_nat(Din(15 downto 8));
                END IF;
            END IF;

            IF rising_edge(write) OR
               falling_edge(OENeg) OR
               ((A'EVENT OR (Din(15)'EVENT AND BYTENeg = '0') OR
                 BYTENeg'EVENT) AND WENeg = '1' AND CENeg = '0' AND
                 OENeg = '0') THEN
                SecAddr <= SA_tmp;
                Address <= A_tmp1;
                
                FOR i IN 0 TO SubSecNum LOOP
                     IF A_tmp1 >= sssa(vs)(i) AND A_tmp1 <= ssea(vs)(i) THEN
                          SubSect <= i;
                     END IF;
                END LOOP;

                CE := CENeg;
                Addr <= A_tmp;
            END IF;
        END IF;
END PROCESS BusCycleDecode;

    ---------------------------------------------------------------------------
    -- Timing control for the Program/ Write Buffer Program Operations
    -- start/ suspend/ resume
    ---------------------------------------------------------------------------
    ProgTime :PROCESS(PSTART, BYTENeg, ESP_ACT, reseted)

        VARIABLE duration : time;
        VARIABLE pob      : time;
        VARIABLE pow      : time;

    BEGIN
        IF LongTimming THEN
            pob  := tdevice_POB;
            pow  := tdevice_POW;
        ELSE
            pob  := tdevice_POB / 2;
            pow  := tdevice_POW / 2;
        END IF;

        IF rising_edge(reseted) THEN
            PDONE <= '1';  -- reset done, programing terminated
        ELSIF reseted = '1' THEN
            IF rising_edge(PSTART) AND PDONE='1' THEN
                IF ( (SA /= VarSect
                    AND Sec_Prot(SA) = '0'
                    AND (Ers_queue(SA) = '0' OR ESP_ACT = '0'))
                    OR (SA = VarSect
                    AND SubSec_Prot(SSA) = '0'
                    AND (Ers_Sub_queue(SSA) = '0' OR ESP_ACT = '0')))THEN

                    IF BYTENeg = '1' THEN
                        duration := pow;--tdevice_POW;
                    ELSE
                        duration := pob;--tdevice_POB;
                    END IF;
                    PDONE <= '0', '1' AFTER duration;
                ELSE
                    PERR <= '1', '0' AFTER 1 us;
                END IF;
            END IF;
        END IF;
END PROCESS ProgTime;

    ---------------------------------------------------------------------------
    -- Timing control for the Erase Operations
    ---------------------------------------------------------------------------
    ErsTime :PROCESS(ESTART, ESUSP, ERES, Ers_Queue, Ers_Sub_Queue, reseted)
        VARIABLE cnt      : NATURAL RANGE 0 TO SecNum+SubSecNum := 0;
        VARIABLE elapsed  : time;
        VARIABLE duration : time;
        VARIABLE start    : time;
        VARIABLE seo      : time;
    BEGIN
        IF LongTimming THEN
            seo  := tdevice_SEO;
        ELSE
            seo  := tdevice_SEO/1000;
        END IF;
        IF rising_edge(reseted) THEN
            EDONE <= '1';  -- reset done, ERASE terminated
        ELSIF reseted = '1' THEN
            IF rising_edge(ESTART) AND EDONE = '1' THEN
                cnt := 0;
                FOR i IN Ers_Queue'RANGE LOOP
                    IF i = VarSect THEN
                        FOR j IN 0 TO SubSecNum LOOP
                            IF Ers_Sub_Queue(j) = '1'
                              AND SubSec_Prot(j) /= '1' THEN
                                cnt := cnt + 1;
                            END IF;
                        END LOOP;
                    ELSIF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN
                        cnt := cnt +1;
                    END IF;
                END LOOP;
                IF cnt > 0 THEN
                    elapsed := 0 ns;
                    duration := cnt* seo;
                    EDONE <= '0', '1' AFTER duration;
                    start := NOW;
                ELSE
                    EERR <= '1', '0' AFTER 100 us;

                END IF;
            ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN
                elapsed  := NOW - start;
                duration := duration - elapsed;
                EDONE <= '0';
            ELSIF rising_edge(ERES) AND EDONE = '0' THEN
                start := NOW;
                EDONE <= '0', '1' AFTER duration;
            END IF;
        END IF;
END PROCESS;

    ---------------------------------------------------------------------------
    -- Main Behavior Process
    -- combinational process for next state generation
    ---------------------------------------------------------------------------
    StateGen :PROCESS(write, Addr, D_tmp0, ULBYPASS, PDONE, EDONE, HANG,
                      CTMOUT_out, START_T1_out, reseted, READY_out, PERR, EERR)

        VARIABLE PATTERN_1         : boolean := FALSE;
        VARIABLE PATTERN_2         : boolean := FALSE;
        VARIABLE A_PAT_1           : boolean := FALSE;

        --DATA  High Byte
        VARIABLE DataHi           : NATURAL RANGE 0 TO MaxData := 0;
        --DATA Low Byte
        VARIABLE DataLo           : NATURAL RANGE 0 TO MaxData := 0;
    BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------
        IF falling_edge(write) THEN
            DataLo    := D_tmp0;
            PATTERN_1 := (Addr = 16#555#) AND (DataLo = 16#AA#) ;
            PATTERN_2 := (Addr = 16#2AA#) AND (DataLo = 16#55#) ;
            A_PAT_1   := ((Addr = 16#555#) AND (ULBYPASS = '0'))
                         OR (ULBYPASS = '1');
        END IF;
        IF reseted /= '1' THEN
            next_state <= current_state;
        ELSE
        CASE current_state IS
            WHEN RESET          =>
                IF falling_edge(write) THEN
                    IF (PATTERN_1)THEN
                        next_state <= Z001;
                    ELSIF ((Addr=16#55#) AND (DataLo=16#98#))THEN
                        next_state <= CFI;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN Z001           =>
                IF falling_edge(write) THEN
                    IF (PATTERN_2) THEN
                        next_state <= PREL_SETBWB;
                    ELSE
                        next_state <= RESET;
                    END IF;
                END IF;

            WHEN PREL_SETBWB    =>
                IF falling_edge(write) THEN
                    IF (A_PAT_1 AND (DataLo = 16#20#)) THEN
                        next_state <= PREL_ULBYPASS;
                    ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN