am29lv160d.vhd

在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d）

        VARIABLE TD_WENeg_CENeg_R      : VitalTimingDataType;

        VARIABLE Tviol_CENeg_OENeg     : X01 := '0';
        VARIABLE TD_CENeg_OENeg        : VitalTimingDataType;

        VARIABLE Tviol_BYTENeg_CENeg   : X01 := '0';
        VARIABLE TD_BYTENeg_CENeg      : VitalTimingDataType;

        VARIABLE Pviol_RESETNeg   : X01 := '0';
        VARIABLE PD_RESETNeg      : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_CENeg      : X01 := '0';
        VARIABLE PD_CENeg         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_WENeg      : X01 := '0';
        VARIABLE PD_WENeg         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_A0         : X01 := '0';
        VARIABLE PD_A0            : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation        : X01 := '0';
    BEGIN

    ---------------------------------------------------------------------------
    -- Timing Check Section
    ---------------------------------------------------------------------------
    IF (TimingChecksOn) THEN
        -- Setup/Hold Check between A and CENeg
        VitalSetupHoldCheck (
            TestSignal      => A,
            TestSignalName  => "A",
            RefSignal       => CENeg,
            RefSignalName   => "CE#",
            SetupHigh       => tsetup_A0_CENeg,
            SetupLow        => tsetup_A0_CENeg,
            HoldHigh        => thold_A0_CENeg,
            HoldLow         => thold_A0_CENeg,
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_A0_CENeg,
            Violation       => Tviol_A0_CENeg
        );
        -- Setup/Hold Check between A and WENeg
        VitalSetupHoldCheck (
            TestSignal      => A,
            TestSignalName  => "A",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            SetupHigh       => tsetup_A0_CENeg,
            SetupLow        => tsetup_A0_CENeg,
            HoldHigh        => thold_A0_CENeg,
            HoldLow         => thold_A0_CENeg,
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_A0_WENeg,
            Violation       => Tviol_A0_WENeg
        );
        -- Setup/Hold Check between BYTENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => BYTENeg,
            TestSignalName  => "BYTENeg",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            SetupHigh       => tsetup_A0_CENeg,
            SetupLow        => tsetup_A0_CENeg,
            HoldHigh        => thold_A0_CENeg,
            HoldLow         => thold_A0_CENeg,
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_BYTENeg_WENeg,
            Violation       => Tviol_BYTENeg_WENeg
        );
        -- Setup/Hold Check between DQ and CENeg
        VitalSetupHoldCheck (
            TestSignal      => DQ0,
            TestSignalName  => "DQ",
            RefSignal       => CENeg,
            RefSignalName   => "CE#",
            SetupHigh       => tsetup_DQ0_CENeg,
            SetupLow        => tsetup_DQ0_CENeg,
            HoldHigh        => thold_DQ0_CENeg,
            HoldLow         => thold_DQ0_CENeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_DQ0_CENeg,
            Violation       => Tviol_DQ0_CENeg
        );
        -- Setup/Hold Check between DQ and WENeg
        VitalSetupHoldCheck (
            TestSignal      => DQ0,
            TestSignalName  => "DQ",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            SetupHigh       => tsetup_DQ0_CENeg,
            SetupLow        => tsetup_DQ0_CENeg,
            HoldHigh        => thold_DQ0_CENeg,
            HoldLow         => thold_DQ0_CENeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_DQ0_WENeg,
            Violation       => Tviol_DQ0_WENeg
        );
        -- Hold Check between CENeg and RESETNeg
        VitalSetupHoldCheck (
            TestSignal      => CENeg,
            TestSignalName  => "CE#",
            RefSignal       => RESETNeg,
            RefSignalName   => "RESET#",
            HoldHigh        => thold_CENeg_RESETNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CENeg_RESETNeg,
            Violation       => Tviol_CENeg_RESETNeg
        );
        -- Hold Check between OENeg and RESETNeg
        VitalSetupHoldCheck (
            TestSignal      => OENeg,
            TestSignalName  => "OE#",
            RefSignal       => RESETNeg,
            RefSignalName   => "RESET#",
            HoldHigh        => thold_CENeg_RESETNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_RESETNeg,
            Violation       => Tviol_OENeg_RESETNeg
        );
        -- Hold Check between WENeg and RESETNeg
        VitalSetupHoldCheck (
            TestSignal      => WENeg,
            TestSignalName  => "WE#",
            RefSignal       => RESETNeg,
            RefSignalName   => "RESET#",
            HoldHigh        => thold_CENeg_RESETNeg,
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENeg_RESETNeg,
            Violation       => Tviol_WENeg_RESETNeg
        );
    -- Setup/Hold Check between BYTENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => BYTENeg,
            TestSignalName  => "BYTE#",
            RefSignal       => CENeg,
            RefSignalName   => "CE#",
            HoldHigh        => thold_BYTENeg_CENeg,--5ns
            HoldLow         => thold_BYTENeg_CENeg,
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_BYTENeg_CENeg,
            Violation       => Tviol_BYTENeg_CENeg
        );

    -- Hold Check between OENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => OENeg,
            TestSignalName  => "OE#",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            HoldHigh        => thold_OENeg_WENeg,--toeh
            CheckEnabled    => PDONE = '0' OR EDONE = '0',--toggle
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_WENeg_R,
            Violation       => Tviol_OENeg_WENeg_R
        );

    -- Hold Check between OENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => OENeg,
            TestSignalName  => "OE#",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            SetupHigh       => tsetup_OENeg_WENeg,--0
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_OENeg_WENeg_F,
            Violation       => Tviol_OENeg_WENeg_F
        );
        -- Hold Check between WENeg and OENeg
        VitalSetupHoldCheck (
            TestSignal      => CENeg,
            TestSignalName  => "CE#",
            RefSignal       => OENeg,
            RefSignalName   => "OE#",
            HoldHigh        => thold_CENeg_WENeg,--0
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CENeg_OENeg,
            Violation       => Tviol_CENeg_OENeg
        );
        -- Setup/Hold Check between CENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => WENeg,
            TestSignalName  => "WE#",
            RefSignal       => CENeg,
            RefSignalName   => "CE#",
            SetupLow        => tsetup_CENeg_WENeg,--0
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENeg_CENeg_F,
            Violation       => Tviol_WENeg_CENeg_F
        );
        -- Setup/Hold Check between CENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => WENeg,
            TestSignalName  => "WE#",
            RefSignal       => CENeg,
            RefSignalName   => "CE#",
            HoldLow         => thold_CENeg_WENeg,--0
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENeg_CENeg_R,
            Violation       => Tviol_WENeg_CENeg_R
        );
        -- Setup/Hold Check between CENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => CENeg,
            TestSignalName  => "CE#",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            SetupLow        => tsetup_CENeg_WENeg,--0
            CheckEnabled    => TRUE,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CENeg_WENeg_F,
            Violation       => Tviol_CENeg_WENeg_F
        );
        -- Setup/Hold Check between CENeg and WENeg
        VitalSetupHoldCheck (
            TestSignal      => CENeg,
            TestSignalName  => "CE#",
            RefSignal       => WENeg,
            RefSignalName   => "WE#",
            HoldLow         => thold_CENeg_WENeg,--0
            CheckEnabled    => TRUE,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_CENeg_WENeg_R,
            Violation       => Tviol_CENeg_WENeg_R
        );

    -- PulseWidth Check for RESETNeg
        VitalPeriodPulseCheck (
            TestSignal        => RESETNeg,
            TestSignalName    => "RESET#",
            PulseWidthLow     => tpw_RESETNeg_negedge,
            CheckEnabled      => TRUE,
            HeaderMsg         => InstancePath & PartID,
            PeriodData        => PD_RESETNeg,
            Violation         => Pviol_RESETNeg
        );
        -- PulseWidth Check for WENeg
        VitalPeriodPulseCheck (
            TestSignal        => WENeg,
            TestSignalName    => "WE#",
            PulseWidthHigh    => tpw_WENeg_posedge,
            PulseWidthLow     => tpw_WENeg_negedge,
            CheckEnabled      => TRUE,
            HeaderMsg         => InstancePath & PartID,
            PeriodData        => PD_WENeg,
            Violation         => Pviol_WENeg
        );
        -- PulseWidth Check for CENeg
        VitalPeriodPulseCheck (
            TestSignal        => CENeg,
            TestSignalName    => "CE#",
            PulseWidthHigh    => tpw_WENeg_posedge,
            PulseWidthLow     => tpw_WENeg_negedge,
            CheckEnabled      => TRUE,
            HeaderMsg         => InstancePath & PartID,
            PeriodData        => PD_CENeg,
            Violation         => Pviol_CENeg
        );
        -- PulseWidth Check for A
        VitalPeriodPulseCheck (
            TestSignal        => A(0),
            TestSignalName    => "A",
            PulseWidthHigh    => tpw_A0_negedge,
            PulseWidthLow     => tpw_A0_negedge,
            CheckEnabled      => TRUE,
            HeaderMsg         => InstancePath & PartID,
            PeriodData        => PD_A0,
            Violation         => Pviol_A0
        );

        Violation := Tviol_A0_CENeg       OR
                     Tviol_A0_WENeg       OR
                     Tviol_BYTENeg_WENeg  OR
                     Tviol_DQ0_CENeg      OR
                     Tviol_DQ0_WENeg      OR
                     Tviol_CENeg_RESETNeg OR
                     Tviol_OENeg_RESETNeg OR
                     Tviol_WENeg_RESETNeg OR
                     Tviol_BYTENeg_CENeg  OR
                     Tviol_OENeg_WENeg_F  OR
                     Tviol_OENeg_WENeg_R  OR
                     Tviol_CENeg_OENeg    OR
                     Tviol_WENeg_CENeg_F  OR
                     Tviol_WENeg_CENeg_R  OR
                     Tviol_CENeg_WENeg_F  OR
                     Tviol_CENeg_WENeg_R  OR
                     Pviol_RESETNeg       OR
                     Pviol_WENeg          OR
                     Pviol_CENeg          OR
                     Pviol_A0             ;